Academic Journal of Science and Technology ISSN: 2771-3032 | Vol. 12, No. 3, 2024 239 Ethernet's Impact on PCB Design and Solutions Xiaoyin Wang1, a 1Teradyne (Shanghai) Co., Ltd., Shanghai (201206), China ayorkwilliam@163.com Abstract: Ethernet is a technology that connects computers to form a local network through which devices can communicate with other devices. For example, 800 GBE (800 Gigabit Ethernet) is a high-speed network technology in the Ethernet standard that supports 800 Gbit/s (800 gigabit per second) data transfer rate. However, over the years, Ethernet has developed into a worldwide data communication system, with speeds ranging from the original 10 Mbit/s to 800 Gbit/s and even 1.6 Tbit/s today. In this context, the complexity of PCB (printed circuit board) chip test design continues to increase. Keywords: Ethernet, worldwide, 800 Gbe, 1.6T, PCB. 1. Introduction In a shared network, when two or more connected devices attempt to send a packet simultaneously over a shared copper or optical cable, the electrical or optical signals that make up the packet (used to represent binary bits in the packet, such as 1s and 0s) overlap, causing the packet to clash and not be able to transmit information smoothly. Therefore, a rule is needed to ensure that information is transmitted correctly and efficiently between devices. Ethernet technology provides this rule. Therefore, High-speed data transmission has become a fundamental requirement for data centers, enterprise networks and telecommunications infrastructure, so Ethernet applications are becoming more and more widespread. However, as Ethernet speeds increase, PCB design faces great technical challenges, especially in terms of signal integrity, thermal management, power control, and physical design layout. These challenges directly impact system reliability, efficiency, and performance. This article focuses on these challenges and strategies to deal with them. 2. PCB Design Is Facing Huge Challenges for The Development of Ethernet 2.1. In high-speed Ethernet applications, signal integrity (SI) is a central challenge in PCB design. High-speed signal transmission makes the signal lines on the PCB more susceptible to electromagnetic interference, reflection, crosstalk, and insertion loss, resulting in signal distortion or loss. Reflection usually results from a mismatch between the impedance of the transmission line and the source or load impedance, causing the signal to reflect and affecting its quality. Crosstalk, because the distance between high-speed transmission lines is too close, electromagnetic interference is generated, which affects the stability of data transmission. In addition, the increase in transmission frequency will lead to more significant insertion losses and signal attenuation, especially over long distances. Inefficient signal transmission in high-speed circuit boards might affect the system’s overall functionality and reliability.[1] Figure 1 depicts how noise hampers signal quality. Figure 1. A signal with noise waveform at the receiver. [1] 240 2.2. Thermal Management The power density produced by high-speed Ethernet systems is significantly high, causing heat buildup on the PCB. Excessive temperature rises can negatively impact the performance and longevity of chips and other components, potentially leading to system malfunctions. As transmission speeds increase, efficient heat dissipation has become a critical factor in PCB design. Over half of all electronic components now fail due to some stress stemming from heat.[2] Consequently, electronic devices are becoming faster and are being deployed in increasingly challenging environments. Integrated circuits (ICs) and surface-mount devices (SMDs) are smaller than ever before, operating at higher frequencies and requiring more power. As the demand for current increases, the voltage drop across resistance components converts electrical energy into heat, causing a rise in temperature and the formation of hot spots. 2.3. The cost of energy consumption is huge While the high-speed efficiency of Ethernet has improved data transmission capabilities, the accompanying increase in power consumption has created significant challenges, especially in data centers and telecommunications infrastructure. With the increasing number of devices and computing needs, energy costs have become a significant expense burden. Therefore, PCB design should not only meet the needs of high-speed data transmission, but also reduce power consumption to ensure the balance of expenditure. 3. PCB Design Solutions for Ethernet High-speed Applications 3.1. Good signal integrity in PCB layout design is based on a well-established set of design rules and constraints. In this article we discuss the introduction of grounding planes into PCB design strategies. Effective grounding plane design involves several key techniques. The continuous ground plane minimizes the use of through-holes in high-speed signal pathways, helping to reduce parasitic effects. In multilayer PCBS, the use of multilayer grounding can significantly reduce ground rebound and enhance signal integrity. In addition, ground plane segmentation should be minimized to avoid impedance discontinuities that cause signal reflection. For example, in high-frequency RF circuits, maintaining a continuous ground plane under the RF signal ensures a stable return path and reduces noise, thereby maintaining signal integrity. These practices are critical to maintaining the performance and reliability of high-speed PCBS. 3.2. Common methods for PCB cooling Engineers generally consider cooling in the design. Passive cooling and active cooling. Passive cooling is best suited for situations where the ambient temperature is significantly lower than the operating temperature of the system, because large, large temperature differences contribute to effective heat dissipation. In this way, engineers can use technologies such as copper pads, splicing holes and heat sinks to effectively transfer heat away from critical components. However, if passive cooling methods are not enough, active cooling methods, such as fans or liquid cooling systems, must be used to rate the heat generated by the device. Active cooling provides an auxiliary cooling method in cases where the passive method cannot be sufficiently cooled. Especially in high-performance applications. The common way is the way of fan and liquid cooling. Liquid cooling systems are suitable for demanding environments such as high performance computing 3.3. Reducing Power Consumption in High- Speed Ethernet PCB Design In high-speed Ethernet PCB design, reducing power consumption is critical to improving overall energy efficiency. A key strategy is to select low-power components, especially in Ethernet controllers and switches, that are designed to minimize energy use and significantly reduce total system power consumption. In addition, dynamic power management technology enables PCBS to regulate power consumption according to different workloads, ensuring energy savings without the need for full system performance. This ensures more efficient operations, especially during periods of low demand or slack. In addition, the high-power component adopts a multiphase power supply design, which can reduce the power loss in the distribution process and further improve the power supply efficiency. Together, these strategies contribute to the development of energy-efficient, high-performance Ethernet systems while also reducing operating power costs. Currently, there are three main energy-saving strategies in 1/10Gbps Energy Efficient Ethernet (EEE). One of these strategies is frame transmission. Among these strategies, the frame transmission [3] method stands out as the most straightforward. Its primary concept involves switching the port to a low-power state when no data is being transmitted, and waking it up when a new data frame arrives. Once the data transfer concludes, the port moves from its active state back into a low-power mode through a sleep cycle. A timer begins as soon as the port enters the low-power state, ensuring that if a new frame arrives before the timer expires, the port will immediately wake up. If no data arrives by the time the timer runs out, the port will still wake up and return to the active state. The EEEP strategy [4], introduced in 2017, adjusts timer parameters dynamically to accommodate changes in network load. As illustrated in Figure 3, it examines historical traffic patterns during each cycle and uses models like the autoregressive moving average (ARMA) to forecast the number of incoming data frames for the next cycle. Based on this prediction, it calculates the time required to transfer those frames and ensures that the energy-efficient Ethernet port exits its low-power state in time to handle the expected traffic, allowing adequate time for the transmission of anticipated data frames. 4. Conclusion With the rapid development of Ethernet technology, PCB design faces multiple challenges in high-speed data transmission environments, including signal integrity, thermal management, and power optimization. Through high- tech means, PCBS can maintain efficient and stable working performance in high-speed Ethernet applications. With the continuous advancement of technology, PCB design will 241 gradually develop in a more efficient and intelligent direction to support future high-speed Ethernet communication systems. References [1] Bahl, D. (2024, October). Printed Circuit Engineering: Understanding Signal Integrity in High-Speed PCBs. Printed Circuit Engineering Association Magazine. https://digital.pcea.net/issues/october-2024/bahl/ [2] Cadence PCB Solutions. (2022). PCB design for thermal performance: Solutions and best practices. Cadence. https://resources.pcb.cadence.com/blog/2022-pcb-design-for- thermal-performance-solutions-and-best-practices [3] REVIRIEGOP, HERNANDEZJ A, LARRABEITID, et al. Performance evaluation of energy efficient ethernet ［J］. IEEE Communications Letters, 2009, 13（9）: 697 - 699. [4] CENEDESEA, TRAMARINF, VITTURIS. An energy efficient ethernet strategy based on traffic prediction and shaping [J]. IEEE Transactions on Communications, 2017, 65 (1): 270 - 282.