187 Circuit Techniques for Overcoming Gain-Bandwidth Limitations in Amplifiers Maiqi Liu 1, * and Yuying Ren 2 1 Dalian University of Technology, Dalian, China 2 Southwest Petroleum University, Chengdu, China * Corresponding Author Email: galaxy_timeless@mail.dlut.edu.cn Abstract. This paper provides a comprehensive review of five core amplifier architecture: Cascode, Cascade, Gain Boosting, Current Cancellation, and Bootstrapping, which aims at breaking through the limitation of Gain-Bandwidth Product in modern electronical systems. Facing the demands of 5G/6G mobile communication, radar detection and medical imaging, this study systematically analyzes the principle, structure and performance of multiple techniques, clarifying its improvement effect on aspects such as gain, bandwidth, output impedance and stability. A comparative assessment of these architectures reveals their respective advantages in different application scenarios and process conditions. Furthermore, the paper also indicates that combining these circuits with FinFET and three-dimensional heterogeneous integration, will emphasize their combined potential to significantly boost linearity, noise performance, and power efficiency. The study also addresses ongoing challenges and future directions in implementing these techniques in mass production environments. These advancements offer critical support significant potential for next-generation high-frequency and high-precision amplifier designs, paving the way for more efficient and reliable electronic systems in emerging technological domains. Keywords: Amplifier gain; cascode; cascade; gain boosting; current cancellation; bootstrapping. 1. Introduction Driven by the advancement of fifth generation (5G) and the transition towards sixth generation (6G) mobile communications, high-performance radar detection, and advanced medical imaging, the demand for broadband high gain amplifiers of modern electronic systems exhibits explosive growth. In communication systems, the base station RF front-end must deliver over 30dB of gain across a bandwidth exceeding 1GHz to support high-speed data links in complex environments. In phased array radars, amplifiers must simultaneously offer high gain and wide bandwidth to enable long-range detection of weak targets and multi-frequency scanning. All these applications impose stringent demands on amplifier performance. However, traditional amplifiers are constrained by the gain-bandwidth product (GBW), making it challenging to extend bandwidth while maintaining high gain—particularly in scenarios such as millimeter-wave bands (e.g., 28 GHz) and ultra-wideband radar systems (1–18 GHz). The GBW bottleneck remains one of the key factors limiting the development of RF integrated circuits and high- performance electronic systems. Therefore, overcoming the limitations of the existing gain-bandwidth tradeoff and developing novel amplifier architecture and design methodologies have become central topics in both academic research and engineering applications. Systematic organizing research breakthroughs in aspects such as current topology, new semiconductor technology and cross-disciplinary integration methods, have a profound impact on promoting next-generation communication, detection and biomedical imaging technology development. This study aims at providing an overview on current state of development broadband high gain amplifiers, analyzing the advantages and disadvantages of mainstream technological routes and prospecting for future development directions. 188 2. Principle of Amplifier Gain Amplifier gain is the basic indicator to measure the amplification capability of the input signal of amplifiers, usually defined as ratio of input signal to output signal. According to the signal type, gain can be categorized into voltage gain, current gain and power gain, etc. In operational amplifiers (op- amp), voltage gain is the most commonly used parameters, whose expression is: 𝐺 = 𝑉𝑜𝑢𝑡 𝑉𝑖𝑛 (1) In this expression, 𝐺 represents gain, 𝑉𝑜𝑢𝑡 represents output voltage, and 𝑉𝑖𝑛 is the input voltage. In practical applications, negative feedback network is often used for controlling te gain of op-amps to stabilize it within the desired range, because of extremely high open-room gain of op- amps (typically reachable values range from 104 to 106, and may even exceed these figures). The magnitude of the gain not only depends on the circuit structure of amplifier itself but also affected by configuration method of external components such as resistor and capacitance. For example, the gain is defined by the ratio of feedback resistance to input resistance in inverting amplifiers. While in in-phase amplifiers, the gain is related to the feedback network and the resistance ratio of the input stage. In addition to static gain, frequency also has an influence on the gain that cannot be ignored. Amplifier gain decreases with the increase in frequency because of parasitic capacitance and inductance in it. This characteristic is usually described as Gain-Bandwidth Product (GBP), and the indicator generally remains constant within a certain frequency range. Therefore, high-gain amplifier design must balance the relationship between gain and bandwidth to avoid signal distortion in high- frequency applications. Additionally, factors such as temperature, power supply voltage fluctuations, and load variations can also affect gain stability. Therefore, in practical circuit design, techniques like temperature compensation, power supply rejection ratio (PSRR), and common-mode rejection ratio (CMRR) are employed to enhance gain accuracy and stability. In short, amplifier gain is one of the core metrics in amplifier gain design. Understanding and optimizing involves multiple dimensions, including circuit topology selection, frequency response analysis, and stability assessment. This forms the foundation for achieving high-performance amplifier circuits. 3. Organization of the Text 3.1 Cascode Cascade circuits represent one of the core techniques for achieving high gain in operational amplifier design. Their principle involves significantly enhancing output impedance through the superposition of transistors, thereby yielding voltage gain far exceeding that of simple common- source or common-drain configurations [1]. The basic circuit is illustrated in Fig. 1. Fig 1. Basic cascode circuit. (Picture credit: Original) 189 This technology is widely used in all kinds of operational amplifier architectures. For example, in Folded-Cascode operational amplifier, it not only provides high gain, but also maintains good frequency and swing of output [2]. In order to optimize frequency performance further, cascode structure is usually combined with advanced Miller compensation technique in application. For example, in fully differential two-stage op-amp, connecting compensation capacitor to common source common gate node, can change or eliminate right half plane zero point efficiently, expanding bandwidth [1]. In low voltage low power field, cascode is also vital. Research successfully achieved a gain of 40 dB, with total power dissipation only 112nW, by applying cascode current mirror as active load in 180 nm CMOS craft subthreshold op-amp [3]. In addition, cascode is indispensable in accomplishing high-precision performance indicators. In Track-to-Track input design, stable bias circuits need accurate circuit copies. High output impedance of cascode circuit mirror can ensure the bias current stable, not influenced by length modulation effect, then maintain constant transconductance (Gm) in the whole common mode range [2]. In high gain, high swing output pole design, the combination of cascode and Class-AB is proved to be an efficient scheme. One design with a 0.35 μm process achieving a gain of over 96 dB is a good example of it [4]. While in a design which pursues a very high gain-bandwidth product (GBW) and slew rate, researchers combined cascode, Adaptive Biasing and Feedback Technology, GBW of the new structure can be 9 times of traditional cascode structure according to reports [4]. Lastly, high output impedance characteristics of cascode structure benefit reducing sensitivity of the subsequent gain stage to the offset voltage, for its boosting effect decreases contribution coefficient of mismatch of threshold voltage in mirror nodes (ΔVth) to general disorder, which is an important factor in optimizing precision [5]. 3.2 Cascade Cascade structure is widely applied in high performance operational amplifier design for its advantages in gain, bandwidth and output impedance enhancement. In multiple papers, cascade is applied in input pole, output pole or whole structure, to optimize comprehensive performance of amplifiers. The basic circuit is shown in Fig. 2. Fig 2. Basic cascade circuit. (Picture credit: Original) In Rail-to-Rail operational amplifier design, cascade input pole is utilized for improving transconductance (Gm), then increase DC gain, without adding the area significantly [6]. For example, a design combines PMOS input pole and cascade current mirror, realizing Common - Mode Rejection Ratio (CMRR) [7]. Another research enhanced GBW and slew rate (SR) further, by combining cascade structure and local common mode feedback (LCMFB) [8]. 190 In output pole design, cascade structure is always combined with Class-AB output pole, in order to support greater output swing and current drive capability [7]. One high gain amplifier treats cascade common source pole as second level, coordinated with Miller compensation capacitor, realizing more than 90 dB gain and hundreds of MHz bandwidth [9]. Furthermore, cascade structure is used in increasing power supply rejection ratio (PSRR) and reducing noise, demonstrating exceptional performance, especially in low power consumption and high gain subthreshold operational amplifier design [10]. In power compensation, high impedance characteristics of cascade node are used in pole separation, combining Feed-Forward Compensation technology, expanding bandwidth further and improving phase margin [11]. One OTA design successfully boosts unity gain bandwidth to 4.5 MHz, meanwhile controls power consumption at 3.15 μW [11]. In summary, cascade structure plays a significant role in modern operational amplifier design, showing strong design flexibility especially in realizing multi-objective optimization such as high gain, high bandwidth, high stability and low power compensation. 3.3 Gain Boosting Gain boosting is a technique that significantly enhances the open-loop gain of amplifiers through local feedback structures, widely used in high-precision analog integrated circuits. This technique achieves high gain by boosting output impedance while maintaining low power consumption. In gain-boosted OTA structures, the gain boosting technique is applied to a continuous-time auto- zeroing amplifier (CTAZ), achieving a loop gain of 130 dB and an input offset voltage of only 2 µV through the use of a differential difference amplifier (DDA) and a gain-boosted OTA. This design, implemented in a 0.18 µm CMOS process, consumes only 27 µW under a 1.8 V supply voltage [12]. A cascode gain-boosting compensation structure proposes a two-stage operational amplifier employing a cascode gain-boosting structure. By introducing a gain stage (M6) in the feedback path of the Miller compensation capacitor, the unit gain bandwidth is significantly increased to 236 MHz, while achieving a gain of 92.5 dB and an ultra-low power consumption of 50 µW [13]. The basic circuit is shown in Fig. 3. Fig 3. Differential Difference Amplifier schematic [12]. Gain boosting technology can also be combined with bulk-driven structures to overcome threshold voltage limitations in low-voltage design. In a structure combining bulk-driving with partial positive feedback, the transconductance of the bulk-driven input stage is enhanced via a partial positive feedback structure, further improving gain and common-mode rejection ratio (CMRR) [14]. Furthermore, a cross-coupled stage structure proposed in another work further enhances 191 transconductance and gain without increasing area. It is suitable for very low voltage (0.5 V) and ultra-low power (70 nW) applications [15]. Although gain boosting improves performance, it increases design complexity and requires careful balancing of stability and power consumption. Future research could focus on the optimization of multi-stage gain boosting structures, compatibility with advanced process nodes, and applications in biomedical and sensor systems. 3.4 Current Cancellation This technique in CMOS operational amplifier design aims to eliminate the right-half-plane (RHP) zero introduced by Miller compensation, thereby optimizing the amplifier's frequency response characteristics. Hurst et al. proposed embedding a cascode current buffer unit in the compensation path of a fully differential operational amplifier. This structure blocks the signal path directly coupling from the input stage to the output, transforming the original RHP zero into a left-half-plane (LHP) zero beneficial for stability, while also pushing the frequency of the secondary pole higher and increasing the unit gain bandwidth [16]. Analysis shows that this method significantly improves phase margin without altering the position of the dominant pole. The basic circuit is illustrated in Fig. 4. Fig 4. Small-signal differential-mode (DM) half-circuit [16]. Palumbo et al. implemented current buffering using a current mirror structure. A cross-coupled current mirror network forms the current control unit. Through precise adjustment of the current ratio, this structure can not only cancel the detrimental feedforward current but also proportionally reduce the value of the compensation capacitor, potentially saving chip area [17]. However, this scheme is more complex in handling common-mode signals and may introduce additional noise. Other research achieved stabilization of the transconductance value through bias circuit optimization. This scheme uses a level-shifting circuit to make the operating regions of the tail currents for the complementary input pair overlap, ensuring minimal variation in the total gm across the entire input voltage range (e.g., below ±4%), while also enhancing common-mode rejection capability and frequency response consistency [18]. In summary, cleverly designing the current path within the compensation network to cancel or steer feedforward currents is a feasible method for constructing high-performance, high-stability CMOS operational amplifiers, particularly suitable for analog and mixed-signal integrated circuits with low supply voltage and high precision requirements. 3.5 Bootstrapping This technique extends the performance boundaries of low-voltage analog circuits by dynamically adjusting internal node potentials. It is particularly suitable for ultra-low voltage applications requiring wide input/output swing. In a 0.4V fully differential OTA design, the Bhatkar team employed adaptive biasing technology, achieving dynamic current boosting through a cross-coupled structure. This design operates in the weak inversion region, maintains an ultra-low power consumption of 4.78 μW, and achieves a gain of 51.15 dB and a bandwidth of 876.5 kHz [19]. Its innovation lies in achieving a near rail-to-rail input range through a bootstrapping mechanism. The Panchal research group combined Bootstrapping with DTMOS technology to implement a variable gain amplifier under a 0.5V supply. Using a combined bulk-gate driving approach 192 significantly reduced the threshold voltage impact, achieving 78.35 dB open-loop gain with 8.35 μw power consumption [20]. This design approach provides a new implementation path for ultra-low voltage analog circuits. The basic circuit is shown in Fig. 5. Fig 5. Dynamic Threshold Amplifier [20]. The HSMC technique proposed by Park et al. implements a super source follower function in the transient response through a dual current buffer structure. Test results show that this technique increases the slew rate to 30 V/μs while reducing the settling time by 240%, greatly enhancing dynamic response performance under large capacitive loads. In summary, bootstrapping technology can effectively solve design challenges in low-voltage analog circuits. Future work could further explore its combination with novel device structures to promote the development of ultra-low voltage analog integrated circuits. 4. Comprehensive Evaluation 4.1 Improved Parameters All the five methods have advantages and disadvantages, and Table 1 lists comparison on the improved parameters of the five amplifier methods. Table 1. Comparison of the improved parameters of different amplifier gain methods. Parameters [21] [3] [9] [10] [22] [23] [24] [25] [26] Supply Voltage (V) 3.3 0.8 1.8 0.5 — 1.6- 5.5 5 1 0.5 MOS Technology (μM) 0.5 0.18 0.13 0.18/0.09/0.045 0.25-0.6 0.25 0.18 0.09 0.18 DC Gain (dB) Slew Rate (V/μS) UGB (MHz) — — 3 40 0.005 0.114 55 38.66 120 74.21 (90nm) 0.033 (45nm) 0.03162 (90nm) — 59.7- 266.66 — — 0.7 1.5 106 — 43 54.53 — 1.7 78.35 0.00714 0.355 5. Conclusion This study systematically reviews the gain principles of five core amplifier structures: cascaded structures, gain-boosting structures, current-canceling structures, and bootstrap structures. Through in-depth analysis of topologies, application scenarios, and performance derivations of gain-doubling circuits, this research elucidates the intrinsic mechanisms for overcoming GBW limitations. Specifically: Cascade structures enhance output impedance and frequency response by optimizing topologies and reducing parasitic capacitance; Cascade structures achieve total gain multiplication 193 through multi-stage amplification; Gain enhancement techniques further boost gain without sacrificing bandwidth by adjusting core parameters like transconductance (Gm); Current cancellation and bootstrap techniques further optimize high-frequency performance by eliminating parasitic capacitance effects and enhancing input impedance, respectively. All these approaches not only achieve synergistic enhancement of gain and bandwidth but also provide critical insights for practical circuit design. Furthermore, integrating these circuit techniques with advanced processes like FinFET and 3D heterogeneous integration will significantly elevate overall amplifier performance, offering robust technical support and theoretical foundations for cutting-edge applications such as 5G/6G communication systems and high-performance radar detection. Authors Contribution All the authors contributed equally, and their names were listed in alphabetical order. References [1] P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram and K. C. Dyer, "Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 275-285, Feb. 2004, doi: 10.1109/TCSI.2003.820254. [2] S. Sakurai and M. Ismail, "Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage," in IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 146-156, Feb. 1996, doi: 10.1109/4.487991. [3] C. Yadav and S. Prasad, "Low voltage low power sub-threshold operational amplifier in 180nm CMOS," 2017 Third International Conference on Sensing, Signal Processing and Security (ICSSS), Chennai, India, 2017, pp. 35-38, doi: 10.1109/SSPS.2017.8071560. [4] Guang, Yang & Bin, Yu. (2012). Design and Analysis of a High-Gain Rail-To-Rail Operational Amplifier. Procedia Engineering. 29. 3039-3043. 10.1016/j.proeng.2012.01.436. [5] C. Stancu, D. Dobrescu and L. Dobrescu, "Offset Voltage Reduction Methods for a Two-Stage Folded Cascode Operational Amplifier," 2022 14th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), Ploiesti, Romania, 2022, pp. 1-4, doi: 10.1109/ECAI54874.2022.9847308. [6] A. Sharma, T. Sharma and B. Kaur, "Rail-to-rail two stage CMOS operational amplifier: A comparative analysis," 2018 2nd International Conference on Inventive Systems and Control (ICISC), Coimbatore, India, 2018, pp. 152-160, doi: 10.1109/ICISC.2018.8399056. [7] A. J. Kumar, K. L. Krishna, K. A. Viswateja, K. Gopi, S. M. Rao and B. Mamatha, "A High Gain Low Power Operational Amplifier using Class AB Output Stage," 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2019, pp. 409-413, doi: 10.1109/ICCMC.2019.8819814. [8] A. Yen and B. J. Blalock, "A High Slew Rate, Low Power, Compact Operational Amplifier Based on the Super-Class AB Recycling Folded Cascode," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020, pp. 9-12, doi: 10.1109/MWSCAS48704.2020.9184559. [9] M. Kadam, "Dual Stage CMOS Operational Amplifier Design in Sky-Water 130nm Technology," 2021 International Conference on Advances in Computing, Communication, and Control (ICAC3), Mumbai, India, 2021, pp. 1-5, doi: 10.1109/ICAC353642.2021.9697325. [10] S. Nitundil, N. Singh, R. Balaji and P. Arora, "Design and Comparative analysis of a Two-Stage Ultra- Low-Power Subthreshold Operational Amplifier in 180nm, 90nm, and 45nm technology," 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 2021, pp. 36-40, doi: 10.1109/DevIC50843.2021.9455791. [11] S. I. Singh, "Design of low-voltage CMOS two-stage operational transconductance amplifier," 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Mysuru, India, 2017, pp. 248-252, doi: 10.1109/ICEECCOT.2017.8284677. 194 [12] V. Raghuveer, K. Balasubramanian and S. Sudhakar, "A 2μV low offset, 130 dB high gain continuous auto zero operational amplifier," 2017 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2017, pp. 1715-1718, doi: 10.1109/ICCSP.2017.8286685. [13] E. Kargaran, H. Khosrowjerdi and K. Ghaffarzadegan, "A 1.5 v High Swing Ultra-Low-Power Two Stage CMOS OP-AMP in 0.18 µm Technology," 2010 2nd International Conference on Mechanical and Electronics Engineering, Kyoto, Japan, 2010, pp. V1-68-V1-71, doi: 10.1109/ICMEE.2010.5558594. [14] J. M. Carrillo, G. Torelli, R. Perez-Aloe Valverde and J. F. Duque-Carrillo, "1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage," in IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 508-517, March 2007, doi: 10.1109/JSSC.2006.891717. [15] Z. Qin, A. Tanaka, N. Takaya and H. Yoshizawa, "0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 11, pp. 1009-1013, Nov. 2016, doi: 10.1109/TCSII.2016.2539081. [16] P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram and K. C. Dyer, "Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 275-285, Feb. 2004, doi: 10.1109/TCSI.2003.820254. [17] G. Palmisano and G. Palumbo, "A compensation strategy for two-stage CMOS opamps based on current buffer," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 44, no. 3, pp. 257-262, March 1997, doi: 10.1109/81.557376. [18] Minsheng Wang, T. L. Mayhugh, S. H. K. Embabi and E. Sanchez-Sinencio, "Constant-g/sub m/ rail-to- rail CMOS op-amp input stage with overlapped transition regions," in IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp. 148-156, Feb. 1999, doi: 10.1109/4.743758. [19] A. N. Bhatkar, M. B. Mali and P. P. Deshmukh, "A 90nm low power OTA using adaptive bias," 2015 International Conference on Pervasive Computing (ICPC), Pune, India, 2015, pp. 1-5, doi: 10.1109/PERVASIVE.2015.7086981. [20] D. Panchal and A. Naik, "0.5 V Variable Gain Amplifier Using Dynamic Threshold MOS for Ultra-Low Power Applications," 2022 IEEE Delhi Section Conference (DELCON), New Delhi, India, 2022, pp. 1-5, doi: 10.1109/DELCON54057.2022.9752924. [21] F. Esparza-Alfaro, S. Pennisi, G. Palumbo and A. J. Lopez-Martin, "Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 8, pp. 574-578, Aug. 2014, doi: 10.1109/TCSII.2014.2327390. [22] N. V. Butyrlagin, N. N. Prokopenko, E. M. Savchenko and A. S. Budyakov, "Design Features of High- Speed CMOS Differential Difference Operational Amplifiers at Low Static Current Consumption," 2018 26th Telecommunications Forum (TELFOR), Belgrade, Serbia, 2018, pp. 1-4, doi: 10.1109/TELFOR.2018.8611965. [23] C. Stanescu et al., "A Dual Low Voltage Chopper Offset-Stabilized Operational Amplifier," 2021 International Semiconductor Conference (CAS), Romania, 2021, pp. 129-132, doi: 10.1109/CAS52836.2021.9604191. [24] T. Mai, K. Schmid, J. Röber, A. Hagelauer and R. Weigel, "A fully-differential operational amplifier using a new chopping technique and low-voltage input devices," 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, Georgia, 2017, pp. 74-77, doi: 10.1109/ICECS.2017.8292081. [25] M. A. Dehkordi, S. M. Mirsanei and S. Zohoori, "A CMOS Low-Noise and Low-Power Transimpedance Amplifier," 2021 29th Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, Islamic Republic of, 2021, pp. 107-111, doi: 10.1109/ICEE52715.2021.9544118. [26] D. Panchal and A. Naik, "0.5 V Variable Gain Amplifier Using Dynamic Threshold MOS for Ultra-Low Power Applications," 2022 IEEE Delhi Section Conference (DELCON), New Delhi, India, 2022, pp. 1-5, doi: 10.1109/DELCON54057.2022.9752924.