ap-4-10.dvi Acta Polytechnica Vol. 50 No. 4/2010 The DEPFET Mini-matrix Particle Detector J. Scheirich Abstract The DEPFET is new type of active pixel particle detector. A MOSFET is integrated in each pixel, providing the first amplification stage of the readout electronics. Excellent noise parameters are obtained with this layout. The DEPFET detector will be integrated as an inner detector in the BELLE II and ILC experiment. A flexible measuring system with a wide control cycle range and minimal noise was designed for testing small detector prototypes. Noise of 60 electrons of the equivalent input charge was achieved during the first measurements on the system. Keywords: DEPFET, BELLE II, ILC, silicon pixel detector. 1 Introduction Accelerator physics experiments use linear or cyclic accelerators to accelerate charged particles. The par- ticles are collided at an interaction point surrounded by various types of particle detectors that track the newly-originated particles. The pixel semiconductor detector near to the interaction point is called an in- ner detector. The DEPFET Collaboration is an inter- national organization developing a new type of pixel semiconductor innerdetector for the InternationalLin- ear Collider andBELLE II, an upgrade of the BELLE experiment in Japan. DEPFET is an abbreviation of ‘DEPleetedFieldEffectTransistor’. Anewsystemhas beendeveloped formeasuring andcharacterizing small samples of the DEPFET detector. This system en- ables precise charge measurements and a flexible high resolution configuration of searing signals. 2 The DEPFET detector 2.1 Active pixel structure The DEPFET detector itself consists of a high- resistivity depleted n-substrate and two p-regions, creating a pnp-sandwich structure (p frontside- implantation, n-substrate, p-rearside). The n-sub- strate is depleted sidewards. The principle of sideward depletion [1, 3] is shown in Fig. 1. The n-substrate (bulk) is depleted from both sides by applying negative voltages to both p- implantationswith respect to the bulk. Theminimum of the electron potential is in a plane parallel to the front surface. Theminimumof the electron’s potential is at depth xmin given by [1] xmin = d 2 + εs qNDd (Vd − Vu) (1) where xmin is the depth of the potential minimum in the detector substrate, q is the elementary charge, ND is the doping concentration of the substrate, d is the total wafer thickness, εs is the dielectric constant of the semiconductor, and Vd, Vu are the voltages ap- plied to the rear and front sides. If Vu = Vd the poten- tial minimum is in the middle. Asymmetric voltages are applied in the DEPFET pixel to shift the electron potential minimum close to the front surface, where theMOSFETis located. Additional n-implantshinder electron lateral diffusion and the electrons are concen- trated in a small region under the MOSFET channel. This region is called an internal gate. Fig. 1: The Principle of Sideward Depletion An impinging radiation generates electron-hole pairs in the depleted n-substrate (bulk), the holes drift to the rearside contact, and the electrons are trapped in the internal gate. The internal gate is located di- rectly under the MOSFET channel below the external 70 Acta Polytechnica Vol. 50 No. 4/2010 gate contact, so the charge stored in the internal gate affects the MOSFET channel. For a fixed drain to source voltage VDS and a constant external gate volt- age VGS, the drain current ID is proportional to the stored charge in the internal gate. The amplification gq is given by the change of the transistor current δID due to the collected charge δQ [1] gq = δID δQ ∣∣∣∣ VGS ,VDS . (2) Amplification 300–600 pA/e− is obtained for mini- matrices with channel effective length 4 μm. Fig. 2: The DEPFET Pixel Cross-section 2.2 Clearing process When new charge collection is needed, it is necessary to empty the internal gate. For clearing out the inter- nal gate, there is a clear contact next to theMOSFET transistor. Fig. 3. showsaCleargatecross-section, and a detailed description of the clearing process is given in [4, 5] and [6]. The electrons are extracted from the internal gate by applying ahighpositive voltage to the clear contact. This causes the electrons drift to the clear contact, where they are taken away. To prevent losses during charge accumulation, the n+-region be- low the clear contact is surrounded by the p-well. The n+-region provides an ohmic contact to the clear elec- trode and with the p-well it provides a reverse biased PN junction that represents a potential barrier for the electrons in the internal gate. When the voltage ap- plied to the clear electrode ishighenough, thedepleted region in the p-well is able to pass through the p-well and touches the p-well boundary (punch-through ef- fect [2]). In this moment there is no barrier for elec- trons in the internal gate and they are extracted. Fig. 3: The Cleargate Cross-section In order to control the potential barrier between the internal gate and the clear contact, an additional MOS structure cleargate is added. If the cleargate is onapositivepotential during the clearprocess, ithelps to formann-channel in the p-well. Butwhereas the n- channel is situated at the surface, the punch-through effect is also effective in thedepths of the internal gate. 3 Measuring system 3.1 Conception TheMini-matrixMeasuringSystem is able tomeasure and characterize a small (3.5 × 3.5 mm) prototype of a DEPFET (see Fig. 4). The small sensor has 4 × 12 active pixels, allowing studies of the DEPFET struc- ture behavior and processes during operation of the sensor. The Mini-matrix readout setup allows us to make a precise collected charge measurement in each pixel with low noise, charge shearing among multiple pixels, clustering, charge-loss measurement, trimming steering voltage values and timing of driving signals. Fig. 4: Photo of the DEPFET Mini-matrix The system is made of commercial and custom- made blocks as a PC with an 8-channel 14-bit 125 Msps PCI data acquisition card, an FPGA con- trol card, a current readout and a switching circuit. The custom-made current readout circuit is made of 8 lownoise trans-impedance readoutamplifiersandthe switching circuit with 12 individual analog switches that are necessary for controlling the gate and clear electrodes of the DEPFET Mini-matrix sensor. Fig. 5: Conception of the Measuring System 71 Acta Polytechnica Vol. 50 No. 4/2010 Theswitching circuit canperformgatevoltage tim- ing with resolution of 7.5 ns. A voltage for a pedestal current subtraction is reconfigurable. The measuring system is controlled and configured by the PC. All 8 channels aredigitizedby14-bitADCswith 125Msps for each channels in parallel with frame readout time 26 us. 3.2 Processing the signals from the detector The readout signals from the DEPFET detector are the current base. The source of the MOSFET pixel is kept at the groundpotential and theMOSFET’s drain is at −5 V. The output signal has two components, constant pedestal current and signal current propor- tional to the charge in the internal gate. The pedestal current is subtracted at the analog level at the inputs of the low noise readout amplifiers. The drain signal currents are read out by 8 amplifiers in parallel and digitized by a GaGe Octopus data acquisition card with 8 14-bit/125 Msps inputs. Fig. 6: The Stream of 8 Drain Signal Currents Fig. 6 shows the typical digitized stream of illumi- natedDEPFETmatrix. The signal stream is recorded and acquired by the data acquisition system (DAQ). 3.3 Low-noise current readout amplifiers The system has 8 parallel current readout amplifiers that consist of 3 parts: TIA, the non-inverting oper- ational amplifier (EL2126), and the fully differential output buffer (AD8139), which can be configured as differential or single-ended. The measured input-referred equivalent noise cur- rent of the readoutamplifiers is 18nARMS.Thenoise is reduced to 8.1 nARMSby using a 4-sample averag- ing method, and to 3.2 by 10-sample averaging. Aver- aging of 90 samples is used in the DAQ system. The noise contribution of the amplifiers is less than 3.6 nA, which is 1 ADU of the 14-bit digitizing system. Fig. 7: Scheme of the Current Readout Amplifier Fig. 8: Photo of the Current Readout Amplifier Board 3.4 DEPFET matrix steering The Mini-matrix DEPFET sensor requires 6 external gate channels and 6 clear switching channels that are controlled by the FPGAcard and configured via a PC program with time resolution of 7.5 ns. Three addi- tional trigger channels are available forADCcard syn- chronization. The external gate electrodes areused for addressing the rows of thematrix. The clear electrode is used to clear one row of pixels. Fig. 9: Scheme of the Double-throw Switch Fig. 9 shows a one channel scheme of the switch. Each channel consists of 1/4 of the ADG1434 analog switch and galvanic separator ADuM1100 insulating FPGA card digital control inputs. The readout frame scheme is very flexible and can be configured to fit current requirements. The FPGA 72 Acta Polytechnica Vol. 50 No. 4/2010 generates drivingpulses according to the configuration software. Fig. 10 shows the structure of the whole matrix readout frame configured in the control program, and Fig. 11 shows the real control channel scopeplots. The frame length is approx. 26 μs. The GATE ON signals are approx. 100 ns overlapping for eachmatrix row to make a continuous drain current flow. This prevents saturation of the amplifiers. Fig. 10: Sequencer Configuration Software Fig. 11: ScopePlots of theExternalGateChannel (above) and Clear Channel (below) 3.5 DAQ Control Monitor Fig. 12 displays the results of the DAQ control moni- tor. The frame is triggered by a hardware trigger gen- erated by the sequencer. The whole frame is recorded and the signals for each row are software-triggered. Samples are taken before and after the clear signal. The evaluated areas are indicated by blue stripes in the ‘Full monitor with soft triggers’ top left window in Fig. 12. Complete data set can be saved in ASCII format with: ADU, hexadecimal or mV float formats. The top middle window is the signal histogram and the top right window indicates the distance between the hardware triggers. The bottom row of windows contains, from the left: real acquired signals in mV, the histogram of the evaluated areas and the evalu- ated parts of the signals. The DAQ control monitor helps to set the software triggers. Fig. 12: The DAQ Control Monitor A visualization tool also forms part of the DAQ Control Monitor. The window in Fig. 13 left shows the real pixel layout and the signal response in ADU units of the14-bit resolutionADC.1ADUcorresponds approximately to a charge of 6 electrons. The noise of each pixel is indicated in the right window. The noise of the matrix in the dark expresses the total system noise. The total noise of all pixels is less than 10ADU, which is a charge of 60 electrons. Fig. 13: The Matrix Signal Response and Noise Visualiza- tion Fig. 14: A Photo of the Measuring System 73 Acta Polytechnica Vol. 50 No. 4/2010 4 Conclusions A measuring system has been designed for the DEPFET Mini-matrix particle detector. The matrix of thedetectorwith4×12pixels canbe repeatedly read out with frame frequency of 38 kHz and noise lower than 60 electrons. The steering pulses can by config- ured with high resolution of 7.5 ns. These parameters are efficient enough to start testing and characteriz- ing the prototypes of the DEPFET particle detector. The development of the second measuring system has already started. Noise below 20 electros should be achieved with the new measuring system. Acknowledgement The research reported on in this paper has been su- pervised by Dr. P. Kodyš, IPNP CUNI in Prague and Prof. M. Husák, FEE CTU in Prague. The research has been supported by the Czech Grant Agency under grantNo. P203/10/0777“Development of the Pixel Semiconductor Detector DEPFET for New Particle Experiments” and by the Grant Agency of the Czech Technical University in Prague, grant No. SGS10/075/OHK3/1T/13 “Testing and Charac- terization of a Mini-matrix DEPFET Particle Detec- tor” References [1] Trimpl,M.: Design of a current based readout chip and development of DEPFET pixel prototype sys- tem for the ILC vertex detector.PhDThesis, Bonn University, 2005. [2] Chu, J. L.: Thermionic injection and space-charge- limited current in reach-throughp+np+structures. Journal of Applied Physics, 1972. [3] Niculae, A. S.: Development of a low noise analog readout for aDEPFET pixel detector.PhDThesis, Siegen University, 2003. [4] Andricek, L., Fischer, P., Heinzinger, K., et. al.: TheMOS-TypeDEPFETPixel Sensor for the ILC Environment.Nuclear Instruments andMethods in Physics Research. Elsevier Science, 2003. [5] Gartner, K., Richter, R.: DEPFET sensor design using anexperimental 3ddevice simulator.Nuclear Instruments and Methods in Physics Research. El- sevier Science, 2006. [6] Sandoe,C.,Andricek,L., Fischer,P., et. al.: Clear- performance of linear DEPFET devices. Nuclear Instruments and Methods in Physics Research. El- sevier Science, 2006. About the author Ján SCHEIRICH was born in 1983. He was awarded a bachelor degree in electronics and telecom- munication in 2006 and a master degree in electronics and photonics in 2008 from FEE CTU in Prague. He attended CERN Summer School in 2007. He is now working towards his PhD at the Department of Mi- croelectronics at the Czech Technical University and at the Institute of Particle and Nuclear Physics at Charles University in Prague. He is a member of the DEPFET Collaboration, the BELL II Collaboration, and the ATLAS Experiment at CERN. Ján Scheirich E-mail: jan.scheirich@cern.ch Dept. of Microelectronics Faculty of Electrical Engineering Czech Technical University Technická 2, 166 27 Praha, Czech Republic Institute of Particle and Nuclear Physics Charles University V Holešovičkách 2, Praha, Czech Republic 74