AP06_5.vp Notation p, n hole and electron density (cm�3) � electrostatic potential (V) NA, ND ionized donor and acceptor density (cm �3) �s permittivity of semiconductor (AsV �1m�1) q elementary charge (As) Jp, Jn current densities (Acm �2) R, G recombination and generation rate (cm�3s�1) �p, �n carrier mobilities (cm 2V�1cm�1) �p, �n quantum correction potentials (V) �p, �n band parameters (V) Dp, Dn diffusion coefficients (cm 2s�1) Tp, Tn carrier temperatures (K) kB Boltzmann constant (eVK �1) Sp, Sn energy flux densities (Wcm �2) E electric field strength (Vcm�1) TL lattice temperature (K) �wp, �wn energy relaxation times (s) mp, mn carrier effective masses (kg) � reduced Planck’s constant (Js) �p, �n quantum correction coefficient �p, �n thermal conductivities (WK �1cm�1) 1 Introduction Double-Gate (DG) MOSFETs are considered to be a promising candidate for nanoscale CMOS. The International Technology Roadmap for Semiconductors (2005 Edition) predicts printed gate lengths up to 15 nm for the next ten years. For these gate lengths conventional MOSFETs are lim- ited due to different short channel effects. On the other hand structures with two gates and an extremely thin body demon- strate better control of the gate region and consequently suppression of short channel effects. Numerical device simulation is an important procedure for the design and optimization of novel semiconductor devices. Some advantages are that the electrical behavior iscalculated before the fabrication process, non-measurable inner-electronic values can be calculated and visualizated, and cost effectiveness due to diagnosis/fault-detection in the technological process. 2 Simulation models Quantum hydrodynamic (QHD) models, which are based on a quantum fluid dynamic model, offer new ways to under- stand and design quantum sized semiconductor devices. The advantage of this model is its macroscopic character, which enables us obtain description without knowing of quantum mechanical details like the initial wave function [1], [2], [3]. The classical hydrodynamic (HD) model for semiconduc- tor device simulation can be extended by expressions in the transport equations and in the energy balance equations. These describe an internal quantum potential in the trans- port equation as well as a quantum heat flux in the energy balance equation. These additional terms in the classical hydrodynamic model allow us to describe the continuous electron and hole distribution in a semiconductor device, accumulations of carriers in potential wells and resonant tunneling of carriers, respectively. The standard model for universal device simulations is the drift-diffusion (DD) model, which can be derived from the above mentioned model [4]. Basic equations of the QHD model are the Poisson equation � �� � � � � � �� �s D A( ) ( )q p n N N (1) continuity equations (index p: holes, index n: electrons) � � � � � � � � �Jp q R G p t (2) � � � � � � � � �Jn q R G n t (3) transport equations Jp p p p p B p p� � � � � � � �q p D q p k p T� � � �( ) ( ) ( ) (4) Jn n n n n B n n� � � � � � � �q n D q n k n T� � � �( ) ( ) ( ) (5) © Czech Technical University Publishing House http://ctn.cvut.cz/ap/ 35 Acta Polytechnica Vol. 46 No. 5/2006 Numerical Simulation of Nanoscale Double-Gate MOSFETs R. Stenzel, L. Müller, T. Herrmann, W. Klix The further improvement of nanoscale electron devices requires support by numerical simulations within the design process. After a brief description of our SIMBA 2D/3D-device simulator, the results of the simulation of DG-MOSFETs are represented. Starting from a basic structure with a gate length of 30 nm, the model parameters were calibrated on the basis measured values from the literature. Afterwards variations in of gate length, channel thickness and doping, gate oxide parameters and source/drain doping were made in connection with numerical calculation of the device characteristics. Then a DG-MOSFET with a gate length of 15 nm was optimized. The optimized structure shows suppressed short channel behavior and short switching times of about 0.15 ps. Keywords: Device simulation, semiconductor devices, double-gate MOSFET. energy balance equations � � � � � � � � S J Ep p B p L wp B p B p 3 2 3 2 3 2 1 k p T T k t pT k T R G � ( ) ( ) 2 1 2 q p G R q t p� � �p wp p� � � � � � � � �( ) ( ) (6) � � � � � � � � S J En n B n L wn B n B n 3 2 3 2 3 2 1 k n T T k t nT k T R G � ( ) ( ) 2 1 2 q n G R q t n� � �n wn n� � � �� � �� �( ) ( ) (7) energy flux density equations S J Jp p p B p p p p� � � � �� �( )T k q T 5 2 3 2 (8) S J Jn n n B n n n n� � � � �� �( )T k q T 5 2 3 2 (9) and equations for the quantum correction potential � � p p p � � �� 2 2 6 m q p p (10) � � n n n � ��2 2 6 m q n n (11) Further approaches are necessary for carrier mobilities, generation and recombination rates, diffusion coefficients and energy relaxation times, which are almost material de- pendent. Equations (1) to (11) are solved self-consistently for the variables ( �, p, n, Tp, Tn, �p, �n). If equations (10) and (11) are neglected, i. e., for �p � �n � 0, the QHD model can be re- duced to the conventional hydrodynamic (HD) model. If the carrier temperatures are set to lattice temperature and equations (6) to (9) are neglected, the quantum drift diffusion (QDD) model and additionally for �p � �n � 0 the conven- tional drift diffusion (DD) model can be obtained. Solutions of the equations are achieved by a successive algorithm (the so called Gummel algorithm). For solving the partial differential equations a box method is used. The resulting non-linear equation systems are solved by the NEWTON-method and the corresponding linear equation systems by preconditioned gradient methods. All models are implemented fully three- -dimensionally in the SIMBA program system [5], [6]. 3 Basic structure simulation and verification The starting point for the simulations is a basic structure represented in Fig. 1, as a functionally relevant detail of the real device. The different parameters are assumed as follows: � gate length LG � 30 nm, � source/drain lengths LS � LD � 100 nm, � gate-to-source and gate-to-drain distances LGS � LGD � 100 nm, � silicon film thickness TSi � 20 nm, � gate oxide thickness Tox � 2 nm, � channel doping NA � 1×10 16 cm�3, � source/drain doping ND � 3×10 20 cm�3. The simulated output characteristics drain current ID versus drain-to-source voltage VDS are plotted in Fig. 2 for 36 © Czech Technical University Publishing House http://ctn.cvut.cz/ap/ Acta Polytechnica Vol. 46 No. 5/2006 Fig. 1: Basic structure of the DG-MOSFET 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 3000 3200 I D A / m [ ] � � VDS V[ ] VGS = 0.4 V VGS = 0.6 V VGS = 0.8 V VGS = 1.0 V VGS = 1.2 V Fig. 2: Output characteristics of the basic structure 0 0.2 0.4 0.6 0.8 1.0 1.2 I D A / m [ ] � � VGS V[ ] VDS = 0.05 V VDS = 1 V Simulation SIMBA[ ] Experiment 7[ ] �0.2 10 �5 10 �4 10 �3 10 �2 10 �1 10 1 10 2 10 3 10 4 0 Fig. 3: Transfer characteristics – Simulation and experiment different gate-to-source voltages VGS. Verification of the simu- lation results and calibration of the model parameters were done by comparison with experimental values from [7]. A structure similar to Fig. 1 with LG � 45 nm, Tox � 2.5 nm, ND � 2×10 20 cm�3 was simulated and compared with the measured values. The results represented in Fig. 3 show good agreement. A further successful verification was done by re- sults from [8]. 4 Parameter variation and optimization To study the influence of the structure parameters on the electrical device characteristics, various parameters are modi- fied. Figs. 4 and 5 depict the output and the transfer charac- teristics at different gate lengths. At shorter gate lengths a threshold voltage roll off can be observed as a typical short channel effect in the particular pinch-off behavior disappears for LG < 30 nm. At the same time, the drain saturation cur- rent increases strongly. Variation results of the silicon film thickness are repre- sented in Fig. 6. Thicker channels lead to larger drain cur- rents, and also to a displacement of the threshold voltage toward smaller values. Therefore the film thickness should be not greater than 20 nm. Thinner gate oxides result in increas- ing drain currents (Fig. 7) and transconductances, and in a better pinch-off behavior. Therefore the smallest possible oxide thickness should be applied. © Czech Technical University Publishing House http://ctn.cvut.cz/ap/ 37 Acta Polytechnica Vol. 46 No. 5/2006 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 3000 4000 I D A / m [ ] � � VDS V[ ] LG = 90 nm LG = 45 nm LG = 30 nm LG = 15 nm LG = 10 nm VGS = 1 V Fig. 4: Output characteristics at different gate lengths 0�0.4 0.8 1.2 I D A / m [ ] � � VGS V[ ] VDS = 1 V LG = 90 nm �0.8 10 �5 10 �4 10 �3 10 �2 10 �1 10 1 10 2 10 3 10 5 0 10 4 0.4 LG = 45 nm LG = 30 nm LG = 15 nm LG = 10 nm Fig. 5: Transfer characteristics at different gate lengths 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 3000 4000 I D A / m [ ] � � VDS V[ ] VGS = 1 V TSi = 30 nm TSi = 25 nm TSi = 20 nm TSi = 15 nm TSi = 10 n m TSi = 5 nm Fig. 6: Output characteristics at different channel thickness 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 3000 4000 I D A / m [ ] � � VDS V[ ] Tox = 1 nm Tox = 1.5 nm Tox = 2 nm Tox = 2.5 nm Tox = 3 nm VGS = 1 V Fig. 7: Output characteristics at different gate oxide thickness Variation of the channel doping causes a decrease in the drain current for doping densities greater than 1017 cm�3 (Fig. 8). The threshold voltage is strongly influenced by doping changes. For optimization of the structures, channel doping can be used to adjust the required threshold voltage. The source/drain doping should be high enough to reduce the series resistances, whereas the dopant diffusion into the channel has to be minimized to prevent short channel effects. In this case rapid thermal annealing processes are an es- sential equirement. Fig. 9 shows the corresponding output characteristics. The knowledge gained from the different variations was used for the design of an optimized structure. A minimal technologically practicable gate length of LG � 15 nm and a gate oxide thickness of Tox � 1.5 nm are specified. Further objectives are threshold voltage of VTh � 0.1 V, large drain saturation current and improved dynamical behavior. After several iterations the further parameters are determined as follows: TSi � 3 nm, NA � 2.8×10 19 cm�3, ND � 7×10 20 cm�3. The resulting output characteristics are represented in Fig. 10. Fig. 11 compares the transfer characteristic of the optimized and basic structure. An enlarged drain current as well as an improved transconductance can be observed. To determine the dynamical behavior, the gate-to-source voltage was switched from 0 V to 1 V to find the turn-on time (tON) and from 1 V to 0 V to find the turn-off time (tOFF). 38 © Czech Technical University Publishing House http://ctn.cvut.cz/ap/ Acta Polytechnica Vol. 46 No. 5/2006 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 3000 4000 I D A / m [ ] � � VDS V[ ] NA = 1×10 cm 17 3� VGS = 1.0 V NA = 1×10 cm 16 �3 NA = 1×10 cm 18 3� NA = 5×10 cm 18 3� NA = 1× 10 cm 19 3� Fig. 8: Output characteristics at different channel doping 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 3000 4000 I D A / m [ ] � � VDS V[ ] ND = 1×10 cm2 1 �3VGS = 1 V ND = 1×10 cm2 0 �3 ND = 1×10 cm 20 �3 ND = 1× 10 cm 20 �3 ND = 1× 10 cm 20 �3 Fig. 9: Output characteristics at different source/drain doping 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1000 2000 2600 I D A / m [ ] � � VDS V[ ] VGS = 0.4 V VGS = 0.6 V VGS = 0.8 V VGS = 1.0 V VGS = 1.2 V Fig. 10: Output characteristics of the optimized structure 0 0.2 0.4 0.6 0.8 1 1.2 I D A / m [ ] � � VGS V[ ] Optimized structure VDS = 1 V Basic structure 10 �5 10 �4 10 �3 10 �2 10 �1 10 1 10 2 10 3 0 10 4 �0.4 �0.2�0.6 �0.8 �1 Fig. 11: Transfer characteristics of the basic and the optimized structure Fig. 12 shows the time response of the drain current. This provides the switching time of tON � tOFF � 0.15 ps. Com- pared with the basic structure the switching times are reduced by a factor of 0.6, primarily due to the structure reduction. 5 Conclusion The scaling down of planar bulk MOSFETs according the International Technology Roadmap for Semiconductors requires new structures such as multiple-gate MOSFETs A promising way to this is with the use of double-gate transis- tors. The implementation will be challenging, with numerous new and difficult issues. In this case numerical device simula- tion is essential. Variations of different structure parameters have been carried out to calculate the influence on device characteristics. Based on these results an optimized structure with a gate length of 15 nm was created. The optimized struc- ture shows suppressed short channel effects and switching times of about 0.15 ps. References [1] Gardner, C. L.: The Quantum Hydrodynamic Model for Semiconductor Devices. SIAM J. Appl. Math., Vol. 54 (1994), No. 2, p. 409–427. [2] Chen, Z.: A Finite Element Method for the Quantum Hydrodynamic Model for Semiconductor Devices. Comput. Math. Appl., Vol. 31(1996), p. 17–26. [3] Wettstein, A., Schenk, A., Fichtner, W.: Quantum Device Simulation with the Density-Gradient Model on Un- structured Grids. IEEE Trans. Electron Devices, Vol. 48 (2001), No. 2, p. 279–284. [4] Selberherr, S.: Analysis and Simulation of Semiconductor De- vices. Berlin, Germany, Springer-Verlag 1984. [5] Klix, W., Stenzel, R.: SIMBA-User Manual http://www.htw-dresden.de/~klix/simba/welcome.html. [6] Höntschel, J., Stenzel, R., Klix, W.: Simulation of Quantum Transport in Monolithic ICs Based on In0.53Ga0.47As-In0.52Al0.48As RTDs and HEMTs with a Quantum Hydrodynamic Transport Model. IEEE Trans. on Electron Devices, Vol. 51 (2004), No. 5, p. 684-692. [7] Lee, J. H., et al.: Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy. IEDM, Tech. Digest, (1999), p. 3.5.1–3.5.4 [8] Vinet, M., et al.: Bonded Planar Double-Metal-Gate NMOS Transistor Down to 10 nm. IEEE Electron Device Letters, Vol. 26 (2005), p. 317–319 Prof. Dr. -Ing. habil Roland Stenzel e-mail: stenzel@et.htw-dresden.de Leif Müller Tom Herrmann Prof. Dr. -Ing. habil Wilfried Klix Department of Electrical Engineering University of Applied Sciences Dresden Friedrich-List-Platz 1 D-01069 Dresden, Germany © Czech Technical University Publishing House http://ctn.cvut.cz/ap/ 39 Acta Polytechnica Vol. 46 No. 5/2006 0.001 0.01 0.1 1.0 10 �20 �10 20 10 I D A / m [ ] � � t ps[ ] VDS = 1 V 0 OFF ( = 1 V 0 V)VGS � ON ( = 0 V 1 V)VGS � Fig. 12: Switching behavior of the optimized structure