id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
ap-1051	Šimeček, I.	Memory Hierarchy Behavior Study during the Execution of Recursive Linear Algebra Library	2008	8	.pdf	application/pdf	2688	156	64	4 Evaluation of the results 4.1 Testing configuration 4.1.1 HW configuration All results were measured on Pentium Celeron M420 at 1.6 GHz, 2GB@ 333 MHz, with the following cache parameters: L1 cache is a data cache with BS � 64, CS � 32 kB, s � 8, h � 64, and LRU replacement strategy. [7]. � For TLB miss ratio measuring, we also used the CA with the following parameters: h �1, s �128, BS � 4096.	cache/ap-1051.pdf	txt/ap-1051.txt