id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
ijassa-1177	Rani, Mucherla Usha; N., Siva Sankar Reddy; B., Rajendra Naik	Leakage Power Reduction in Read and Write Enhanced Macro Memory Circuit Design Using Transistor Stacking and Reversible Approach	2022	18	.pdf	application/pdf	8144	504	67	Here, the initial analysis is carried out by comparing the proposed reversible transistor stacked SRAM cell design with the existing cell designs to prove its efficiency in leakage power reduction. Furthermore, a reversible logic is applied in all the peripheral circuits, which gives additional level of confidence in terms of leakage power.	cache/ijassa-1177.pdf	txt/ijassa-1177.txt