id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
ijassa-359	Sanapala, Kishore; sakthivel, R.	Design of Full Adder Using Subthreshold DTPT Logic	2016	10	.pdf	application/pdf	3287	233	67	Sec- tion 2 presents the brief description about existing full adder designs reviewed in comparison with the proposed design. [Present] 2293 69.25 158.79 From the comparisons in Table2 it is noted that proposed adder has achieved major savings in terms of PDP and is more than 82% lesser than the min3- IJCNN and min3 stacked adder designs, 29.5% lesser than the direct synthesis adder design and also 13.98% lesser than the min3 mirrored adder design.	cache/ijassa-359.pdf	txt/ijassa-359.txt