Design and implementation of a broad band frequency synthesizer Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 15 Design & Implementation of High Switching & Low Phase Noise Frequency Synthesizer Ali M. N. Hassan Information & Communications Engineering Dept. Al Khwarizmi College of Engineering University of Baghdad (Received 14 November 2005; accepted 4 April 2006) Abstract:- This research describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = - 92dBc & spurious -100 dBc The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar & reference divider in single chip. Therefore our system consists of a single chip contains (low phase noise PFD, charge pump, prescalar & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip is used to provide the following properties :  Low power consumption.  Small size, light weight.  Flexibility in selecting crystal oscillator frequencies to fit into the system frequency planning.  High reliability. The application of this synthesizer in frequency hopping systems, satellite communications & radar because it has high switching speed ,low phase noise & low spurious level. 1.Introduction The generation of accurate waveforms plays a crucial role in almost all electronic equipment, from radar to home entertainment equipment. A frequency synthesizer is defined as a system that generates one or many frequencies derived from a single time base (frequency reference), in such a way that the ratio of the output to the reference frequency is a rational fraction. The frequency synthesizer output frequency preserves the long-term frequency stability (the accuracy) of the reference and operates as a device whose function is to generate frequencies that Al-khwarizmi Engineering Journal Al-Khwarizmi Engineering Journal, Vol.2,No.2,pp 15-31 (2006) Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 16 are multiples of the reference frequency (multiples by a single or many numbers). These multiples may be whole or fractions; but since only linear operations are used (in the frequency domain), these numbers can only be rational. A frequency synthesizer, as defined here, can thus generate an output frequency of, say, X/Y (where X and Y are whole numbers) times the reference frequency. PLL synthesizers can be found in the most sophisticated radar systems or the most demanding satellite communications terminals as well as in car radios and stereo systems for home entertainment. The PLL is a feedback mechanism locking its output frequency to a reference. PLL synthesizers gained popularity for their simplicity and economics. Frequency synthesizers use a PLL to copy, multiply, or divide a crystal reference source. The stability and phase noise properties of the crystal reference oscillator are preserved within the loop bandwidth of the PLL[2]. 2.Frequency Synthesizer Requirements The basic requirement set for a frequency synthesizer by any telecommunications system is that the synthesizer must be able to generate all required frequencies with a sufficient accuracy. The output signal of an ideal frequency synthesizer is a pure sinusoid, i.e. a delta function in the frequency domain. The output spectrum of a real synthesizer, however, consists of a number of nonideal components in addition to the sinusoidal component. Figure 2.1 illustrates these components, as well as other parameters, whose specifications will be derived in the following sections. 2.1.Phase Noise It is divided into two types:- 2.1.1Phase noise at small offset frequencies In the transmitter, the major contributor to the phase error is the frequency synthesizer generating the local oscillator frequency. The close-in phase noise manifests itself as random fluctuations in the phase of the local oscillator signal, which then translate directly to fluctuations in the phase of the transmitted signal, i.e. random phase error. Let us assume that the frequency synthesizer is a second-order PLL, i.e. the phase noise rolloff is -40 dB per decade for offset frequencies beyond the loop bandwidth. Let us also assume that the phase noise floor of the synthesizer is low enough to be ignored as a contributor to the total integrated noise. This assumption is only valid for narrow band systems, where the PLL bandwidth is only about an order of magnitude smaller than the channel bandwidth. Let us denote the phase noise at small offset frequencies by L close-in , the phase-locked loop bandwidth by B PLL , and the channel bandwidth of the system in question by B channel . We can now approximate the square of the phase error with[3]. Eq(2.1) Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 17 Solving for the close-in phase noise, we get: Eq (2.2) shows that increasing thePLL bandwidth leads to a tighter specification for the close-in phase noise. 2.1.2.Phase noise at large offset frequencies The phase noise of the frequency synthesizer at large offset frequencies is almost always specified. The reason for this is a phenomenon commonly referred to as reciprocal mixing. The phase noise tail of the local oscillator signal mixes with undesired interfering signals, and the mixing result ends up at the same intermediate frequency as the wanted signal, thus impairing the signal-to-noise ratio. The reciprocal mixing phenomenon is illustrated in Figure 2.2. The spectrum converted to the intermediate frequency can be represented as the convolution of the received RF spectrum and the spectrum of the local oscillator signal (Equation (2.3)). Eq(2.3) Since the interfering component can be much stronger than the wanted signal, the phase noise power of the local oscillator at the same offset frequency must correspondingly be much lower to maintain a useful signal-to-noise ratio of the down converted signal. The specification for the local oscillator power at a given offset frequency can be derived from the power levels of the wanted signal and the interfering signal, and the signal-to-noise ratio required to guarantee signal reception at the desired bit error rate: Eq(2.4) The last term of the equation is an approximation, assuming that the mean value of the phase noise over the channel bandwidth can be approximated with the phase noise value at the center point of the channel. 2.2.Spurious tones Spurious tones are unwanted components in the frequency synthesizer output spectrum that are not noise-like. The VCO is essentially a frequency modulator, and periodic signals at the VCO control line will result in an output signal with discrete FM sidebands. The requirement for the maximum spurious power derives from the blocking specification of the telecommunications Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 18 system. A spurious tone at a given offset mixes the neighboring channel at the same offset down to on top of the wanted channel. The spurious power must therefore be low enough to provide an adequate signal-to-noise ratio (SNR) in the output of the receiver. A number of nonidealities in the PLL itself will generate interfering signals in the VCO control line. All of these phenomena will result in periodic signals at the PLL reference frequency, and thus in spurs at an offset of f ref from the carrier. The dominant spurious-generating nonidealities in a typical PLL are mismatch between the up and down currents in the chargepump and charge injection through the switches in the chargepump. Also, the leakage currents of the chargepump and the VCO may be significant contributors. Figure 2.3 shows how the mismatch between the up and down currents in the chargepump results in a periodic signal in the VCO control line. In this case, the up current is slightly larger than the down current. The PLL feedback mechanism tries to keep the mean value of the VCO control voltage (V C ) constant, and therefore the down pulses from the phase detector will be slightly longer to compensate for the smaller current. The resulting net output current of the chargepump (I CP ) is then low pass filtered in the loop filter. Despite of the filtering, the VCO control voltage still clearly shows a periodic beat at the reference frequency, which will in turn result in spurious tones[4]. The charge injection through the chargepump switches is illustrated in Figure 2.4. The digital up and down signals from the phase detector will have relatively fast rise and fall times, and thus harmonic components at very high frequencies. Some of these high- frequency components will be injected to the chargepump output node through the gate-source and gate-drain capacitances (C GS and C GD ) of the switch transistor. The capacitances C GS and C GD depend on the gate-to-source and gate-to-drain voltages V GS and V GD , respectively. Therefore, the charges injected through the up and down switches will depend on the chargepump output voltage. The up and down charges will be equal for one single output voltage value. For all other output voltages, there will be a net charge injected to the output of the chargepump. The PLL will compensate for this excess charge very much in the same way as the chargepump mismatch in Figure 2.3, and a periodic beat at the reference frequency is generated. The other phenomenon typically generating reference spurs is the loop filter leakage. When the PLL is locked, the chargepump is neither pumping up nor down for most of the time. Ideally, a chargepump in this state represents an infinite impedance towards the loop filter. Likewise, the input impedance of the VCO control node is ideally infinite. In practice, however, both the chargepump switches and the VCO control node (typically connected to a varactor diode) will have finite impedances, and there will be a small leakage current that will change the control voltage of the VCO slightly either up or down. The PLL will compensate for the leakage, and thus a periodic beat at the reference frequency is again generated. In PLL’s using a discrete loop filter, the leakage currents are normally not a problem. The loop filter capacitors are very large, and a small leakage current will change the loop filter voltage only negligibly. Since Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 19 the spurious power will depend on the actual shape of the interfering waveform It is first assumed that the disturbance on the VCO control line appears as narrow, rectangular pulses having a width Δt and a height ΔV. Inserting the Fourier series expansion of the rectangular waveform into the time domain representation of the VCO output waveform yields the following equation for the VCO output: Eq(2.5) Equation (2.5) indicates sidebands at ±nω ref from the carrier, where ω ref is the phase comparison frequency. Typical approaches to reducing the problem are using large capacitors in the loop filter (to keep ΔV to a minimum), and minimizing K VCO to minimize the modulation index. However, both remedies have their downsides as well: increasing the loop filter capacitance requires increasing the chargepump current proportionally; K VCO cannot be lowered indefinitely, because the tuning range still needs to cover the desired frequencies plus process, temperature and supply voltage variations. 2.3.Settling time In modern telecommunications systems, the synthesizer often has strict requirements for settling time, defined as the time it takes for the synthesizer to settle to a given accuracy after a frequency step. In time division multiple access (TDMA) systems, the settling time specification is mostly due to the desire to use the same synthesizer for both transmit and receive modes, thus saving power and area. In frequency hopping systems, the relatively frequent changing of the channel frequency is used to make sure that enough packets are received correctly even if a part of the frequency band would be blocked by strong interferers. Independent of the reason for changing the transmit or receive frequency, the system specifications usually set a limit on how fast this needs to be done, and this can be directly translated into a synthesizer settling time requirement[5]. In the phase-locked loop, being a low- pass control system by nature, the settling time is always inversely proportional to the loop bandwidth. Other constraints, such as stability, reference suppression, and close-in phase noise normally set the upper limit for the loop bandwidth. On the other hand, the settling time specification typically sets the fundamental lower limit. Using the standard notation of feedback theory, a second-order loop has a closed- loop transfer function of Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 20 Eq(2.6) where ξ is the damping factor, and ω n is the natural frequency. From the step response of the closed-loop transfer function we can derive the minimum required natural frequency for the loop to settle within a given maximum relative frequency error δ (absolute frequency error divided by the total frequency step) in a given switching time t sw to be Eq(2.7) Assuming the damping factor ξ to have a value of 0.707 (optimal value in most cases), we can express the minimum loop crossover frequency as Eq(2.8) 3.System Design & Implementation It is required to design of microwave fast hopping frequency synthesizer to use in communications & Radar , that has the following basic requirements:  Frequency range 2.0 – 2.7 GHz  Step size at least 1MHz  Switching time less than 1msec  Spurious o/p -70 dBc  Phase noise @1KHz -50 dBc To achieve the above requirements with lowest cost & complexity , the system design as a single loop PLL frequency synthesizer to obtain the following specifications:  Frequency range 1.5 – 2.75 GHz  Step size 1 MHz  Switching time less than 1msec A schematic diagram of the system is sketched by ADIPLLSIM version(2.7) software as shown in Figure (3.1).The system consists of the following components :  Single chip contains digital PFD(phase frequency detector) ,charge pump, reference divider & prescalar.  Voltage controlled oscillator(VCO) . Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 21  Loop filter.  Reference oscillator. 3.1.Single Chip The single chip consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1).this chip is used for simplifying system architecture and reducing cost. In our system the single chip synthesizer is selected ADF4106 from Analog Device company because it has low phase noise, low spurious & low power consumption. The functional diagram of the single chip is shown in figure (3.2)[10]. The components of the single chip will illustrate as follows:  Phase Frequency Detector (PFD) and Charge Pump: The PFD takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 3.3 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse.  Prescalar(p/p+1): The dual- modulus prescaler (P/P + 1), along with the A counter and B counter, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A counter and B counter. The prescaler is programmable. It can be set in soft-ware to 8/9, 16/17, 32/33, or 64/65. The A counter and B counter, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is Eq(3.1) Where : f VCO is the output frequency of the external voltage controlled oscillator (VCO). P is the preset modulus of the dual- modulus prescaler (8/9, 16/17, etc.). Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 22 B is the preset divide ratio of the binary 13-bit counter (3 to 8191). A is the preset divide ratio of the binary 6-bit swallow counter (0 to 63). f REFIN is the external reference frequency oscillator. For our system the prescalar is programmed to 16/17.  R – counter: The 14-bit R (reference) counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. 3.2.Voltage controlled oscillator The VCO must be cover the range (1.5- 2.75) GHz with lower phase noise. Therefore we select RQRE -1500-27500 from ralton company to satisfy these requirements. It has the following specification:  Tuning voltage ,DC :(1-20)volt.  Typical o/p power : 7 dBm.  D.C. power supply VCC: 10 volt with tolerance ±0.25. 3.3.Reference oscillator The reference oscillator has a frequency 10 MHz & the reference counter (R- counter)in the single chip synthesizer must be set to 100 to obtain on 100KHz step size. 3.4.loop filter design The loop filter is a passive 2nd order filter which is selected in the system because it has the following properties:  the least complex loop filter.  Smallest resistor thermal noise.  Largest capacitor next to VCO to minimize the impact of VCO input capacitance.  Maximum resistance to variation of VCO gain & PFD gain The loop filter impedance is defined as the voltage output at VCO to the current injected at the charge pump in the single chip synthesizer. The expression of loop filter impedance Z(s) & the corresponding poles & zeros are shown below at various filter orders is shown below[1]: Z(s) = (1 + sT2) /( A0(1+sT1)(1 +sT3)(1+sT4)) Eq(3.2) Where A0 is filter coefficient & equal to (c1 + c2) for passive loop filter For passive 2nd order loop filter, the input impedance: Z(s) = (1 +sC2 R1) / (s(C1 + C2)(1 + (sC1C2R1) / (C1 +C2))) Eq(3.3) From the above equations , it should be clear : T2 = R1C2 , T1 = R1 C1 C2/A0 & A0 = C1 + C2. Then C1 = A0 T1/T2 , C2 = A0 - C1 , R1 = T2/C2. T2 = ζ / (wc 2 T1) Where ζ = optimization factor = 1.005 , wc = 2 л Fc, Fc = loop B.W., T1 ={[ (1+ ζ )2 tan2 φ + 4 ζ ]1/2 - (1+ ζ) tan φ}/ (2 wc) , φ = phase margin & A0 = {(K Kvco ) / (Nwc 2)} / {[(1+ wc 2 T22) / (1 + wc 2 T12) ]1/2} for the system : C1 = 12.2 nF , R1 = 5.46 KΩ , & C2 = 12.8 nF 4.Results Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 23 A system is simulated by ADIPLLsim version 2.7 software & we obtain the following results: - 4.1. Phase noise The phase noise of PLL frequency synthesizer & VCO is shown in the following table: Offset frequency (Hz) PLLfrequency synthesizer VCO 100 -92.85 -171.3 1K -92.4 -151.3 10 K -92.74 -131.3 100 K -90.19 -114.8 1 M -117.0 -132.5 The c/c of phase noise with frequency for the system at output frequency 2.03 GHz is shown in figure 4.1 1k 10k 100k 1M 10M Frequency (Hz) -160 -150 -140 -130 -120 -110 -100 -90 P h a s e N o is e ( d B c /H z ) Phase Noise at 2.03GHz The VCO c/c is simulated By ADIsimPLL software is shown in figure 4.2. Figure 4.1. The c/c of phase noise with frequency for the system Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 24 1k 10k 100k 1M 10M Offset Frequency -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 S S B P ha se N oi se (d B c/ H z) VCO Phase Noise at 2.03GHz 0 2 4 6 8 10 12 14 16 18 20 Voltage (V) 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 F re q u e n c y ( G H z) VCO Freq v s Volts 0 2 4 6 8 10 12 14 16 18 20 Voltage (V) 40 50 60 70 80 90 100 110 120 130 K v (M H z/ V ) VCO Kv v s Volts 4.2.Reference Spurious Noise and Jitter Calculations include the first 10 ref spurs First three spurs: -100 dBc -100 dBc -100 dBc 4.3.switching speed the switching speed for Frequency change from 1.5GHz to 2.75GHz is 36.4 µs The transient response for system from 1.5GHz to 1.65 GHz is shown in figure 4.3: Figure 4.2. The c/c of VCO phase noise with frequency, VCO freq. with voltage & VCO Kv with voltage respectively Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 25 0 10 20 30 40 Time (us) 1.50 1.52 1.54 1.56 1.58 1.60 1.62 1.64 1.66 F re q u e n c y ( G H z) Frequency 5.Discussion The operation of implemented synthesizer was verified and various performance parameters have been checked &it is found they are within the system requirements . The first parameter is the phase noise , table 4-1 shows the highest phase noise in the system is -92.74dBc/Hz at 10KHz offset & The over shoot for phase noise @ offset frequency 100 KHz as shown in figure 4.1 results from that the loop B.W. for PLL is 100 KHz. The second parameter is the switching time is shown in figure 4.3 is 36.4 µs is something close to theoretical value (4msec)in section 3.2.2 & the overshoots in figure 4.3 results from the transient case of frequency change & this transient case must be very small in time. The third parameter is a reference spurious , is illustrated from the results is -100dBc & this value satisfy the system requirements for spurious. 6.Conclusions A frequency synthesizer with frequency range (1.5 – 2.75) GHz using single loop frequency synthesizer was design & implement. The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the PFD , prescalar & reference divider in single chip. this single chip has the following properties :  Low power consumption.  Small size, light weight.  flexibility in selecting crystal oscillator frequencies to fit into the system frequency planning.  High reliability. From the results of this research, we conclude that the switching speed can be increase by increase loop bandwidth this results in increasing the reference frequency but it causes in increasing the step size. There are many techniques to implement this system. Figure4.3. The transient c/c of system from 1.5GHz to 1.65GHz Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 26 We would present these techniques with their disadvantages. There is Direct digital synthesis (DDS) can be used to implement this system but it has drawbacks , its main disadvantage include the fundamentals limit of B.W. (maximum frequency o/p is less than one half the clock rate). Expanded B.W. requires higher clock rates , & therefore faster logic and more critical manufacturing & testing processes. There is Hybrid technique (DDS as reference oscillator) can be used to implement this system successfully but it has high cost relative to implemented system. Multi Loop PLL can satisfy this frequency range but these loops with their mixers increase spurious o/p signals , power dissipation , cost , size & complexity. The major benefits of implemented system over the multi loop frequency synthesizer will illustrate in a fair comparison with previous work in 2003 includes design of an integrated CMOS PLL frequency synthesizer consists of two loops. System parameters Frequency range(GHz) Step size Switching time Phase noise Spurious level Number of loops Multi loop implemented In 2003 2.4 – 2.5 1MHz 30 µs -83 dB/Hz @10 KHz -60 dBc 2 System implemented. 1.5 – 2.75 1MHz 36.4 µs -92dB/Hz @10 KHz -100dBc 1 7. References 1. Dean banerjee “PLL performance , simulation & design” 4th edition, 2005. 2. Goldberg, Bar-Giora.,” Digital frequency synthesis demystified”, LLH Dean banerjee “PLL performance , simulation & design” 4th edition, 2005 3. J.A Crawford, “Frequency synthesizer Deign Handbook” , Artech house, Norwood ,1994. 4. J. Craeninkx & M. Steyaert, “Wireless CMOS Frequency Synthesizer Design” Kluwer Boston ,1998. 5. Li Lin, “Design Techniques for High Performance Integrated Frequency Synthesizers for Multi-standard Wireless Communication Applications” UNIVERSITY OF CALIFORNIA , phD, Thesis,2000 Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 27 6. Lascari lance, “Accurate phase noise prediction in PLL frequency synthesizers” Applied Microwave & Wireless , VOL. 12 , No. 5 , May2000 7. Mike Curtin and Paul O’Brien. “Phase locked loops for high frequency receivers and transmitters,” Analog Dialogue Volume 33, 1999. 8. Roland E. Best. “Phase-locked Loops”, McGraw-Hill (1993). 9. Mannassewitsch Vadim “Frequency synthesizers Theory & Design”Third edition, Wiley & sons. New York, 1987. 10. The analog Device ADF41XX series Data sheet,2005. Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 28 Figure 2.2. Reciprocal mixing Figure 2.1. Non ideal components in the output spectrum of a PLL frequency synthesizer. Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 29 Figure 2.4 Charge injection in the chargepump switches. Figure 2.3 periodic signal generated by the charge pump. Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 30 CE 10 DVdd 15 Gnd 9 CP 2 Fin A 6 Ref In 8 NotesADF4106: 1. Vp is the Charge Pump power supply 2. Vp >= Vdd 3. CE must be HIGH to operate 4. TSSOP pinouts shown 5. Consult manufacturer's data sheet for full details MUXOUT 14 Gnd 4 Gnd 9 LE 13 Data 12 Clock 11 AVdd 7 Vp 16 ADF4106 / ADF4107 Gnd 3 Fin B 5 R set 1 Rset 5.10k R1 3.42k C2 12.8nF C1 1.95nF Ct 0F VCO RQRE-1500-2750 V Supply Reference TCXO10 Gnd V+ F out Figure 3.1. Schematic diagram of system Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 31 Figure 3.2. Functional diagram of single chip Figure 3.3. Schematic diagram of PFD & charge pump Ali M. N. Hassan/Al-khwarizmi Engineering Journal ,Vol.2, No. 2 PP 15-31(2006) 32 تصميم وبناء مركب ترددات ذو سرعة تحويل عالية وضوضاء طوري قليل علي محمد نوري قسم هندسة المعلومات واالتصاالت كلية هندسة الخوارزمي / جامعة بغداد :الخالصة يصف هذا البحث تصميم وبناء مركب ترددات باستخدام طريقة اقفال ااطور احادي الدورة وبالمواصفات التالية : .مايكرو 63ميكا هرتز ،زمن تحويل 0( ميكا هرتز، واقل سعة قفزة 0501-0011مدى الترددات الخارجة ) -د الخارج.ومستوى الطفيليات هرتز من الترد 01111ديسبيل عند (92-)ثانية ومستوى ضوضاء طوري ديسبيل 011 كاشف التردد التطور الحاصل في الدوائر المتكاملة جهز البساطة في تصميم مركب الترددات وذلك ألنه دمج والطور ،ومقسم التردد الثنائي ، ومقسم التردد في شريحة رقيقة واحدة. لذلك منظومتنا تتكون من شريحة تحتوي رددات وطور ذو ضوضاء طوري قليل،مضخة شحنة دقيقة،مقسم ترددات مبرمج ، ومقسم كاشف ت(على كل من ( مبرمج( مرشح ترددات واطئة ،مذبذب ترددات ذو سيطرة جهدية، ومذبذب مرجعي. p/( p+1)تردد ثنائي) هذه الشرحة الرقيقة التي تحتوي كل من كاشف ترددات وطور مقسم ترددات مبرمج ومقسم تردد ثنائي تم استخدامها وذلك ألنها تمتلك المواصفات التالية: قلة في استهالك القدرة حجم صغير ووزن خفيف مرونة في اختيار تردد مذبذب البلورة بحيث يناسب خريطة التردد للمنظومة وثوقية عالية ر التطبيقات لهذا المركب في منظومات القفز بالتردد ، واتصاالت األقمار االصطناعية، والرادا وذلك ألنها تمتلك خاصية ضوضاء طوري قليل وسرعة تحويل عالية ومستوى طفيليات اقل.