AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 40 -Qadisiyah Journal For Engineering Sciences . All rights reserved Hardware Implementation of IT2FLC using FPGA for Control Applications Assist. Prof. Dr. Mohammed Y. Hassan University of Technology, Control and Systems Department, Baghdad, Iraq E mail: 60003@uotechnology.edu.iq Saif Faris Abulhail University of Technology, Control and Systems Department, Baghdad, Iraq E mail: saifabulhail80@gmail.com Lecturer Dr.Waleed Fawwaz Shareef University of Technology, Control and Systems Department, Baghdad, Iraq E mail: 60026@uotechnology.edu.iq Received on 4 December 2017 Accepted on 22 January 2018 Published on 14 May 2018 DOI: 10.30772/qjes.v11i1.519 Abstract: Interval Type2 Fuzzy Logic Control (IT2FLC) has been applied to a number of industrial, medical, home and military applications. Hardware implementation of IT2FLC can be achieved in a number of ways. One of these ways is the use of a Field Programmable Gate Array (FPGA). In this paper, the design and implementation of an IT2FLC using FPGA has been presented. The proposed controller is of Mamdani type. It works in different structures (P/PI/PD/PID like IT2FLC) depending on two control lines, different number of triangular shape memberships (2-7) depending on three control lines, six tunable gains and within a range of sampling time of (0.01-1024) seconds. Three type reduction algorithms are used and it is found that the Enhanced Iterative Algorithm with Stop Condition (EIASC) produced the minimum reduction in FPGA size. Thus less execution time. The reduction size is about 75% than Karnick Mendel (KM) and is about 3% than Enhanced KM (EKM). Linear and nonlinear models are used to test the designed Controller. Gains are tuned manually to reach minimum overshoot, settling time and steady state error. Simulation and Implementation results showed that the proposed controller works in an efficient way under no-load, load and uncertainty in the nonlinear model parameters. Keywords: Footprint of uncertainty, Karnick Mendel, Enhanced Karnick Mendel and FPGA mailto:60003@uotechnology.edu.iq mailto:saifabulhail80@gmail.com mailto:60026@uotechnology.edu.iq AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 41 -Qadisiyah Journal For Engineering Sciences . All rights reserved Nomenclatures 1. INTRODUCTION Type2iFLC containifootprintiof uncertaintyi(FOUi) that is able toihandle the numerical uncertainties, nonlinearities and linguisticmassociatedi with the inputs and outputs. Hassan and Sharif [1], in 2006 proposed a Proportional-Integral-Derivative Type1 FLC (PIDT1FLC). Fuzzy sets and programmablemrule table were designed usingmVery High DescriptionmLanguage (VHDL) for implementation on FPGA device. The controller could serve as allProportional-Derivative T1FLC (PDT1FLC), Proportional-Integral T1FLC (PIT1FLC), or Proportional-Integral-Derivative T1FLC (PIDT1FLC). Two versionsllof this controller were designed; the first onellis 6-bits FPGA-Based Design, which uses 6 bits for I/Ollvariables, while the second one is 8-bit FPGAllBased Design, which uses 8 bits.llThe results of the simulation showed that the 8-bit FPGA-Based Design is superior to the 6-bit FPGA-Based Design. Maldonado, et al. [2], in 2011 presented the design of the optimal T2FLC obtained using Genetic Algorithms (GA) for optimization. The optimization of Triangular and Trapezoidal Membership Functions (MFs)llof a fuzzy system is done for hardware representations such as the FPGA. The GA uses only certain points of the MFs, while the fuzzy rules did not Symbols Definition οΏ½ΜƒοΏ½ Type-2 Fuzzy sets 𝑓 𝑛 Upper Firing Level �̃�𝑛 Fuzzy rule number 𝐹 Friction torque 𝐹𝑐 Coulomb friction 𝑔 Gravity 𝐽 Moment of inertia �̃�𝑖 𝑛 Inputs fuzzy sets 𝑒(π‘˜) Sampled error 𝑓 𝑛 Lower Firing Level 𝑦 𝑛 Lower end point 𝑦 𝑛 Upper end point 𝐹𝑛 Firing interval π‘Œπ‘π‘œπ‘  Centre of Sets Type Reduction 𝑦𝑙 Left end point π‘¦π‘Ÿ Right end point R Right switch point 𝐿 Left switch point π‘ˆ Control action πœ‡ �̃�𝑖 𝑛 Lower Membership Function of Input �̃�𝑖 𝑛 πœ‡ �̃�𝑖 𝑛 Upper Membership Function of Input �̃�𝑖 𝑛 𝐽π‘₯ Type1 fuzzy set πΉπ‘‚π‘ˆ(οΏ½ΜƒοΏ½) Upper Footprint of uncertainty AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 42 -Qadisiyah Journal For Engineering Sciences . All rights reserved change. The GA was tested in a T2FLC to regulate the direct current motor speed, using the MATLAB/SIMULINK and VHDL code. Comparisons were made between the T1FLC versus T2FLC, to evaluate the difference in performance of both types of controllers. Mani and Barjeev [3], in 2012 developed the implementation of a T1FLC through the use of the VHDL code. FLC is designed for an armature control DC motor speed control. VHDL has been used to develop FLC on FPGA. A Sugeno type FLC structure has been used to obtain the controller output. The controller algorithm developed, synthesized, simulated and implemented on FPGA Spartan 3E xc3s500e-4fg320llboard. Panda, et al. [4], in 2012lldesigned an IT2FLC for an automaticllvoltage regulator system. For controller design, memberships of system variables are represented using interval value fuzzy sets. Thelleffectiveness of this controller has been investigated through simulation studies. The simulation showed performance of the controller and compared with a PID controller. Jun, et al. [5], in 2014 presented a newllfeed-water controller under thellautomatic power regulatingllsystem for an advancedllboiling waterllreactor. The new feedllwater controller is designed by using a rule-based hierarchicalllFLC and is implemented by using the FPGA technology. The results demonstrated that the FPGA-based hierarchical FLC is a practical approach forllautomatic power operations inlladvanced nuclear power plant applications. Schrieber and Biglarbegian [6], in 2015 developed hardware implementation and performance comparison ofllIT2FLC for real-time applications. IT2FLC with parallel processing usingllFPGA was designed and implemented. Design and implementation are using three different inference mechanisms of IT2FLC on hardware. Li, et al. [7], in 2015 designed sampled data controller for IT2FLC withllactuator fault. The IT2FLC and the IT2 state-feedbackllcontroller share different MFs. It was found that there has not been a major focus on the design and implementation of P/PI/PD/PID like IT2FLC usingllFPGA chip. In this paper, an IT2FLC can work with different number of memberships and several type reduction algorithms with highllresolution data. Several promisingllapproaches havellused other types in the design of controllers. The proposed IT2FLC is designed for controlling efficientlyllto the real systems and to achieved smallllFPGA size and as a result, less execution time must be achieved vs. acceptable accuracy. Hardware setup and experimental results of the linear and nonlinear models are explained. The rest of this paper is organized as follows: section 2 introduces to an IT2FLC and its computations. Section 3 describes the designed controller, including the performing of an IT2FLC with different structures and type reduction algorithms. Section 4 illustrates the implementation and hardware setup of an IT2FLC, including ALTERA DE2 board, National Instrument (NI) 6212 device. It describes the connections between these devices with PC using hardware in the loop approach. Section 5 shows the practical results of the designed IT2FLC that is connecting with linear and nonlinear models. Section 6 presented the conclusions from this work. 1. INTERVAL TYPE2 FLC Type2iFuzzyllsetsimembershipllfunction are fuzzy and contain FOUllthat handles andllmodels the uncertainties, nonlinearities andlllinguistic relatedllwith the inputs and output of the FLC. FOUlis theiarea betweeni lower membership and upper membership. It is allowingieachllinput toihave two membershipllgrade values related with it; an Upper MF (UMF) and Lower MF (LMF). There are two types of T2FLC: Mamdani type and TakagillSugenollKang (TSK) type. The differencellbetween these two types, the Sugeno output membership fucntion is linear or constant and the Mamdani output is shape thellmembership. Mamdani type needs type reducer methodllwhile the Takagi Sugeno type does not need typeireduction operation. The structure of the IT2FLC is shown in Figure (1) [8, 9]. AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 43 -Qadisiyah Journal For Engineering Sciences . All rights reserved Figure 1: Structure of T2FLC. 1.1 COMPUTATIONS OF IT2FLC An IT2FLC icontaining atileast one interval fuzzy set withoutiloss ofigenerality. If an IT2 FLC consisting of Nirules, the rule base has the followingiform: �̃�𝑛 ∢ 𝑦 = π‘Œπ‘› If π‘₯1 is οΏ½ΜƒοΏ½1 𝑛 and … and π‘₯𝐼 is �̃�𝐼 𝑛, where 𝑖�̃�𝑖 𝑛 (𝑖 = 1𝑖 . … . 𝑖𝐼𝑖) are IT2 fuzzyisets. In addition, π‘Œπ‘› = [𝑦 𝑛 𝑖. 𝑦 𝑛 ] is an interval that can be understoodias the centroid of a consequent IT2 fuzzy set or theisimplest TSK model. Each rule consequent is represented by a crisp number in many applications [10]. For an inputivector 𝑋′ = (𝑖π‘₯β€²1 . π‘₯β€²2 . …...𝑖π‘₯′𝐼 ) . Typicalicomputations inian IT2FLC include the followingistepsi[10]: 1) Compute themmembership interval of π‘₯′𝑖 onmeach �̃�𝑖 𝑛 , [ πœ‡ �̃�𝑖 𝑛 (π‘₯ ′𝑖 ) . πœ‡ �̃�𝑖 𝑛 (π‘₯ ′𝑖 )] , 𝑖 =1, 2.…. 𝐼. 𝑛𝑖 =1,2.….iN. 2) Calculate the firing interval of the π‘›π‘‘β„Žirule, 𝐹𝑛: 𝐹𝑛 = [πœ‡ οΏ½ΜƒοΏ½1 𝑛 (π‘₯ β€²1 ) Γ— … Γ— πœ‡ �̃�𝐼 𝑛 (π‘₯ ′𝐼 ) β€š πœ‡ οΏ½ΜƒοΏ½1 𝑛 (π‘₯ β€²1 ) … Γ— πœ‡ �̃�𝐼 𝑛 (π‘₯ ′𝐼 )] ≑ [𝑓 𝑛 . 𝑓 𝑛] . 𝑛 =1,2…N. 3) The thirdmstep is that Performmtype reduction. The mostmcommonly usedi onemis the centeri of sets typeireducer: π‘Œπ‘π‘œπ‘  = βˆ‘ π‘Œπ‘›π‘π‘›=1 βˆ‘ 𝐹𝑛𝑁𝑛=1 = [𝑦𝑙 . π‘¦π‘Ÿ ] (1) 𝑦𝑙 = π‘šπ‘–π‘› π‘˜βˆˆ[1.π‘βˆ’1] βˆ‘ 𝑦 𝑛 𝑓 𝑛 +βˆ‘ 𝑦 𝑛 𝑓𝑛𝑁𝑛=π‘˜+1 π‘˜ 𝑛=1 βˆ‘ 𝑓 𝑛 +βˆ‘ 𝑓𝑛𝑁𝑛=π‘˜+1 π‘˜ 𝑛=1 (2) π‘¦π‘Ÿ= π‘šπ‘Žπ‘₯ π‘˜βˆˆ[1.π‘βˆ’1] βˆ‘ 𝑦 𝑛 𝑓𝑛+βˆ‘ 𝑦 𝑛 𝑓 𝑛𝑁 𝑛=π‘˜+1 π‘˜ 𝑛=1 βˆ‘ 𝑓𝑛+βˆ‘ 𝑓 𝑛𝑁 𝑛=π‘˜+1 π‘˜ 𝑛=1 (3) In equation (2) and equation (3) 𝐾 is a potential switchipoint. 4) Compute themdefuzzified output as: 𝑦 = (𝑦𝑙 + π‘¦π‘Ÿ)/2 (4) 2. CONTROLLER DESIGN The general block diagram of the proposed controller is shown in Figure (2). This proposed IT2FLC is designed by combining the advantages of fuzzy inference and different structures of controller. The type of the controller is selected using two bits selection linesβ€š as illustratedllin Table (1). Structure design of thellproposed IT2FLC is shown in Figure (3). The inputs to the controller are: input-output tunable gainsβ€š AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 44 -Qadisiyah Journal For Engineering Sciences . All rights reserved sampling timeβ€š set-point and the controlllsignal. The output of the controller is the control action signal. The range of thelluniverse of discourse isllwithin [βˆ’1 π‘‘π‘œ 1] for each input and output. The proposed controller can work with (2-7) input-output triangular shaped MFs. The user can select the number of MFs using three control signals (C3β€š C4 and C5) that is listed in Table (2). The shapes of MFs design are shown in Figure (4). The defuzzification technique is selected as Centroid method. The sampling time is selected by user depending on the model that is connecting with the proposed controller. Rule-base is written in a lookup table. This Rule-base is designed by the user and located in the controller. Mamdani- type is used to perform fuzzy inference of the controller. Three algorithms KMβ€š EKM andllEIASC are used to implement the type reduction method of the IT2FLC. EKM has threellimprovements over the KM algorithm. Firstβ€š a betterllinitialization is used to reduce the number of iterations. Thenβ€š the terminationllcondition of the iterations is changed to removellone unnecessarylliteration. Finallyβ€š a subtlellcomputing technique is used to reduce the computational cost oflleach iteration. EIASC algorithmllenumerate the switchllpoint for 𝑦𝑙 from 1llto Nβˆ’1 until 𝑓𝑙(π‘˜) stopslldecreasing, at whichllpoint 𝑦𝑙 is obtained. Similarly, llthey enumeratellthe switch pointllfor π‘¦π‘Ÿ from 1 to Nβˆ’1 until π‘“π‘Ÿ(π‘˜)stops increasing, at which point π‘¦π‘Ÿis obtained. The comparisons among three type reduction algorithms are listed in Table (3). It can be concluded from Table (3) that using EKM algorithm gives small FPGA chip size than KM algorithm and as a result generates less execution time and using EIASC algorithm produces small FPGA chip size than EKM algorithm and as a result generates less execution time. It can be notice that the use of EIASC with the proposed controller give us less FPGA size. Thusβ€š EIASC will be used in the implementation of the IT2FLC. The programs arellwritten using MATLAB / SIMULINK and MATLAB functionsβ€š then converted into VHDL and Verilog formats using HDL coder. HDL coder technique has many restrictions and limitations in MATAB functionsβ€š such as (for loopβ€š if statementβ€š floating point and FIND function). Therefore; these limitationsllwere solved by designing MATLAB functions that overcome the HDL coder restrictions. The program is generated to achieve minimum FPGA size and as a resultβ€š less execution time. Furthermoreβ€š In order to design a PID like IT2FLCβ€šllt.is.required to design..a fuzzy inference system withllthree inputs thatllrepresent the proportionalβ€š derivative andllintegral components. A fuzzyllcontroller with three inputs mayllnot beipreferredβ€š because it islldifficult to design. Foriexampleβ€š if eight fuzzy sets are used for each inputβ€š then a (8*8*8=512) rules willube required for the controller. Insteadβ€š PID likellT2FLC canube designed asia parallelistructure of a PD like IT2FLC and a PI like IT2FLC. The outputiof the PID like IT2FLC is formed byialgebraically summing the outputs of theitwoifuzzy control structure. This method will reduce the number of rules required to (8*8+8*8=128) rules onlyβ€š as shownllin Figure (5). A PD like IT2FLC may be employed to serve as PI like IT2FLCllin incremental form. Equation (5) shows a PDllcontroller equation obtained in a positionllformβ€š while Equation (6) shows a PI controller equation in an incremental form in discrete time domain: 𝑒𝐷(π‘˜) = 𝐾𝑃 𝑒(π‘˜) + 𝐾𝐷 βˆ†π‘’(π‘˜) (5) βˆ†π‘’πΌ(π‘˜) = 𝐾𝑃 βˆ†π‘’(π‘˜) + 𝐾𝐷 𝑒(π‘˜) (6) 𝑒𝐼(π‘˜) = 𝑒𝐼(π‘˜βˆ’1) + βˆ† 𝑒𝐼(π‘˜) (7) βˆ†π‘’(π‘˜) = 𝑒(π‘˜)βˆ’ 𝑒(π‘˜βˆ’1) 𝑇𝑠 (8) where 𝑒𝐼(π‘˜βˆ’1) is the previousllcontrol signalβ€š 𝑒(π‘˜)is allsampled error signalβ€š 𝑒(π‘˜βˆ’1) is a previous sampled errorllsignal βˆ†π‘’(π‘˜) is the ratellof change of sampledllerror signal, 𝑇𝑠 is thellsampling time and index (k) represents the present sampling instant. Now by comparing equations (4) and (5) β€š it show that the PD likellIT2FLC in a position formllbecomes a PI like IT2FLC inllincremental form if 𝑒(π‘˜) and βˆ†π‘’(π‘˜) exchange positionsβ€šllKD is replaced by 𝐾𝐼 and 𝑒𝐼(π‘˜) is replaced by βˆ†π‘’πΌ(π‘˜) . The output of a PI likellIT2FLC is obtained by summing the changellof control signal βˆ† 𝑒𝐼(π‘˜) and the previous control signal𝑒𝐼˳. The outputs of the PD likellIT2FLC and PIlllike IT2FLC are summedlltogether to form the PID like IT2FLC output. Sincelleach PD likellIT2FLC has its ownllgains and rulesβ€š the controller design can act as a P like IT2FLC by setting KD of PD and PI like IT2FLC to zeroβ€š a PD like IT2FLCβ€š a PI likellIT2FLCβ€š and a PIDlllike IT2FLC depending on twollbits control signal C1 and C2 as illustrated previously. AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 45 -Qadisiyah Journal For Engineering Sciences . All rights reserved Figure 2: General block diagram of the controlled system Figure 3: Structure of the proposed controller Three MFs (b ) Two MFs (a) AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 46 -Qadisiyah Journal For Engineering Sciences . All rights reserved Six MFs (d ) Four MFs (C) Five MFs (f)Seven MFs (e) Figure (4): MFs design (a) Three inputs PID like IT2FLC (b) Two inputs PID like IT2FLC Figure 5: Minimizing rule-base of PID like IT2FLC a) b) AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 47 -Qadisiyah Journal For Engineering Sciences . All rights reserved 3. IMPLEMENTATION Of THE PROPOSED IT2FLC 3.1 Altera Development FPGA Board Altera DE2 board is shown in Figure (6), it providesmtwo 40-pin expansion headers. Each headermconnects directly to 36 pins on themCyclone LL FPGA, and also provides DC +5V (VCC5) and two GND pins [11]. Figure 6: ALTERA FPGA board 3.2 NI USB 6212-DAQ Device Data acquisitionllsystems is shown in Figure (7), it incorporate signals, llsensors, actuators, signalllconditioning, data acquisitionlldevices and application software. NI USB-6212 DAQ is a simple and lowllcost multifunction I/Olldevice from National Instruments. Figure 7: NI DAQ 6212 AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 48 -Qadisiyah Journal For Engineering Sciences . All rights reserved 3.3 Hardware Connections The advantage of NI USB 6212 DAQ in this design is to transfer data between the PC and Altera DE2 board. Verilog HDL language is used in Quartus II software program to implement the proposed IT2FLC. Verilog code that represents the proposed IT2FLC is synthesized and downloaded into the FPGA using Quartus II 13.0 web edition software (64-Bits). Quartus II summary report, shown in Figure (8), describes the requirement FPGA gates. The connection between the model and the proposed controller is using hardware in the loop approach as shown in Figure (9), where the model is simulated in MATLAB and the controller is working in FPGA ALTERA DE2 Board. NI USB 6212-DAQ acts as the interfacing between PC and the proposed controller. Linear and nonlinear models are simulated in the MATLAB/ SIMULINK environment. Data Acquisition Toolbox software is installed in (MATLAB 2017a) to provide a set of tools for analog input, analog output, and digital input/output. The controlllaction generated fromllthe proposed controller isllsent to the PCllin a parallel way through NI USB 6212-DAQ device. NI USB 6212-DAQ is sending it in serial mode to the PC usingllUSB port. Thellfeedback signal is returned to the controller through DAQ device using USB port. The required ALTERA DE2 pins are connected with NI USB 6212-DAQ pins using wires. Thirty-two wires are connected between NI USB 6212 DAQ and ALTERA DE2 board, 16 for inputs and 16 for outputs. The pins from (A0 – A15) are setting as output (control action) and (A15 -A31) are setting as input (actual output). Two switches (C1) and (C2) are using to select the type of the proposed controller as illustrated in Table (1). Three switches (C3, C4 and C5) are used to select the number of MFs, see Table (2). One push- Bottom is used to reset the controller. Finally, the photograph of the hardware setup is shown in Figure (10). Figure 8: Quartus II Summary Report Figure 9: Hardware In The Loop Connections AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 49 -Qadisiyah Journal For Engineering Sciences . All rights reserved Figure 10: Connections between NI USB 6212-DAQ and ALTERA DE2 board 4. PRACTICAL RESULTS In order to examinellthis proposed controllerβ€š linear and nonlinear models are used. In this designllsamplinglltimellisllsetlltoll0.01llseconds.Inllorderlltollreachllminimumiovershootβ€šiminimum.undershootβ€š minimum settling timeβ€š minimum steady state error and minimum structure designβ€š trial and error method is used to tune the gains and rules as shown in Table (4) to obtain the best response. The desired position is chosen as a unit step value. Seven Triangular memberships are chosen for testing purposes. 4.1 Linear Model A linear model is selected as an example and represented by the following transfer function: 𝑦(𝑧) = 0.00995𝑧 π‘§βˆ’0.99 (9) Gains are tuned manually and they are listed in Table (5). The unit step response of this model using P like IT2FLC as shown in Figure (11), PD like IT2FLC as shown in Figure (12), PI like IT2FLC as shown in Figure (13) and PID like IT2FLC is shown in Figure (14). AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 50 -Qadisiyah Journal For Engineering Sciences . All rights reserved (a) with no load (b) with load =10% from step input Figure 11: Output time response of the linear model controlled by the P like IT2FLC (a) with no load (b) with load =10% from step input Figure 12 : Output time response of the linear model controlled by the PD like IT2FLC AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 51 -Qadisiyah Journal For Engineering Sciences . All rights reserved (a) with no load (b) with load =10% from step input Figure13: Output time response of the linear model controlled by the PI like IT2FLC (a) with no load (b) with load =10% from step input AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 52 -Qadisiyah Journal For Engineering Sciences . All rights reserved Figure 14: Output time response of the linear model controlled by the PID like IT2FLC 4.2 Nonlinear Servo Motor Model The DC motor is a particular sort of motors, which is classified as one of the principal machines to generate mechanical power from electrical power. The mathematical model of servoimotor system isirepresented by aisecond order dynamic system withifriction as follows [12]: 𝐽π‘₯�̈� = 𝑒𝑖 βˆ’ 𝑖𝐹 βˆ’ 𝑇𝐿𝑖 (10) whereithe moment of inertia is represented by 𝐽 ; the acceleration is represented by �̈� . Theicontrol inputitorque isirepresented by . 𝐹 is the friction torque and 𝑇𝐿 is the load torque. The friction torque is represented by static friction phenomena. Which include: coulomb friction, Stictionifriction, and theiviscousifriction. i.e.. [14]. 𝐹 = {𝐹𝑠 exp (βˆ’ ( οΏ½Μ‡οΏ½ π‘₯οΏ½Μ‡οΏ½ ) 2 ) + 𝐹𝑐 (1 βˆ’ exp (βˆ’ ( οΏ½Μ‡οΏ½ π‘₯οΏ½Μ‡οΏ½ ) 2 )) + 𝜎|οΏ½Μ‡οΏ½|} βˆ— 𝑠𝑔𝑛(οΏ½Μ‡οΏ½) (11) where the coulombifriction is represented by 𝐹𝑐 . the stiction friction isirepresented byi𝐹𝑠 . the stribeck velocity is represented by π‘₯οΏ½Μ‡οΏ½ . and 𝜎 is the viscous friction coefficient [12]. Gains are tuned manually and they are listed in Table (6).The unit step response of this model using PID like IT2FLC without applyinglluncertainty to the system is shown in Figure (15). Moreover, the unit step response with applying uncertainty about 10% from unitllstep input to the friction and moment of inertiallparameters is shown in Figure (16). … (a) with no load (b) with load =10% from step input Figure 15: Output time response of the servo motor controlled by the PID like IT2FLC AL-QADISIYAH JOURNAL FOR ENGINEERING SCIENCES Vol. 11, No. 1 ISSN: 1998-4456 Page 53 -Qadisiyah Journal For Engineering Sciences . All rights reserved (a) with no load (b) with load =10% from step input Figure 16: Output time response of the servo motor with uncertainty parameter of about 10 % controlled by the PID like IT2FLC CONCLUSION In this paper, the P/PI/PD/PID like IT2FLC has been implemented on FPGA chip. This proposed controller is designed to control linear and nonlinear models. Thellpractical results showed that the unit step responsellof nonlinear model controlledllby the proposed controllerllafter changing the uncertainty parameters with 10% was close to response of the same model before this changing. It can be used with industrial, home, medical andllmilitary applications. Thellend user can select sampling time, the structure ofllthe controller, number of membershipslland tune the gainsllonly. REFERENCES 1. M. Y. Hassan and W. F. Sharif.” Design of FPGA based PID like Fuzzy Controller for Industrial Applications”, …0International Journal of Computer Science, 2007. 2. Y. Maldonado. O. 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