id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
american_scientific_journal-3371	Khan, Imtiaj; Morshed, Ovishek; Mominuzzaman, Sharif Mohammad	Performance Study of Strain Engineered CMOS Inverter Logic Using Silicon Nanowire and Carbon Nanotube Field Effect Transistors	2017	11	.pdf	application/pdf	4742	252	58	As switching delay time for a CMOS inverter circuit is related to the velocity saturation effect, a conclusion can be drawn from these curves that for SiNW-FET CMOS inverter, tensile strain increases the switching delay time whereas compressive strain decreases it for high applied field. Here, +1% strain denotes tensile strain whereas −1% strain denotes compressive strain (Figure 1a) and the values of p signify two different types of chiralities as explained in section 2 (Figure 1b).	cache/american_scientific_journal-3371.pdf	txt/american_scientific_journal-3371.txt