28 American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) ISSN (Print) 2313-4410, ISSN (Online) 2313-4402 © Global Society of Scientific Research and Researchers http://asrjetsjournal.org/ Design of GMSK Frequency Hopping Modulation Scheme Based on FPGA Lijun Gea*, Xiaoying Lib, Xiaoxiao Wangc a,b,cSchool of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300387, China aEmail: gelj@mail.nankai.edu.cn bEmail: 1002477935@qq.com cEmail: yan7317@qq.com Abstract An FPGA-based GMSK frequency hopping modulation scheme is designed. The design of the frequency hopping module is added to modulation scheme, and used the digital implementation of GMSK modulation. The pre-encoded symbols are first processed by a Gaussian filter and then sent to a phase accumulator to calculate the accumulated phase. The accumulated phase is summed with the phase generated by frequency-hopping carriers of frequency hopping module to obtain the total phase, and finally we use the CORDIC algorithm to perform the cosine operation on the total phase to realize the GMSK frequency hopping modulation of the signal. This scheme is implemented on the FPGA. After testing and verification, this scheme can realize the frequency hopping function of the system. The design of the phase accumulator ensures the phase continuity of GMSK signal, and the CORDIC algorithm eliminates a large number of multiplication operations. The hardware implementation is simpler and improves the feasibility of the scheme. Keywords: GMSK modulation; frequency hopping communication; FPGA; phase accumulator; CORDIC algorithm. ------------------------------------------------------------------------ * Corresponding author. http://asrjetsjournal.org/ American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 29 1. Introduction In the national defense of security and military war, the role of communication technology is increasingly important, if the transmitted information is discovered by enemy, it will cause an inestimable damage. So, it is necessary to use a communication technology to ensure the validity and security of the communication. Frequency hopping communication is widely used in various strategic and tactical communication systems due to its interference immunity and confidentiality [1]. In the frequency hopping communication, the carrier is pseudo-randomly hopped with the change of the hopping sequence, and the transmission bandwidth is increased, so it is difficult for enemy to intercept data when the enemy is in an unknown hopping rule. Therefore, the frequency hopping communication system has strong interference immunity and high reliability [2]. At the same time, in the frequency hopping communication system, the excellent spectral characteristics and high frequency efficiency of GMSK (Gaussian Minimum Shift Keying) modulation can effectively improve the transmission speed of the system [3]. The existing GMSK modulation generally adopts the orthogonal modulation method of waveform storage. Firstly, the input signal is encoded to generate two orthogonal waveform data, and then the information of the waveform in various phase paths is stored to make a look-up table, and the look-up table method is used to implement GMSK modulation [4]. However, this modulation method does not implement the frequency hopping function of the system, and there is a quadrature phase error of the two tributary signals, which eventually leads to a phase error of the modulated signal, so it cannot ensure the phase continuity of the modulated signal. At the same time the operation of this method is more complicated and requires a lot of storage space. To solve these problems, a new GMSK frequency hopping modulation method is proposed in this paper, which adds the frequency hopping module to the GMSK modulation system, so it can easily realize the control of frequency hopping and increased the security and confidentiality of the frequency hopping system. At the same time, the system can enhance the controllability of frequency hopping, and the GMSK modulation method can ensure the phase continuity of the GMSK signal, simplify the modulation process and save a lot of storage space. 2. Modulation Principle of GMSK GMSK is an improved modulation technique based on minimum frequency shift keying, which means that the input signal need to be preprocessed by Gaussian low-pass filter before modulation[5]. The impulse response expression of the Gaussian low-pass filter is expressed as follows : 2( ) exp ( )h t tp p α α  = −   (1) In equation (1) α is a constant related to the 3dB bandwidth of the transfer function. The Gaussian impulse response of a rectangular pulse of width bT is: American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 30 2 ( / 2) 2 ( / 2)1( ) [ ( ( ] 2 ln 2 ln 2 b b b B t T B t Tg t Q Q T p p− + = − (2) Where function )(xQ is expressed as: 21 1( ) exp( / 2) 22 2x xQ x d erfcτ τ p ∞ = − =∫ (3) In equation (2), B is the 3dB bandwidth of the Gaussian filter, and the input of the Gaussian filter is Bipolar non-return to zero code, the expression is: ( ) ( )n bm t a b t nT= −∑ (4) Where    ≤ =±= else 0 2/0 /1 )(,1 bb n TtT tba so the output signal of the Gaussian low-pass filter is: ( ) ( )* ( ) ( )n bX t m t h t a g t nT= = −∑ (5) In summary, the final output of the GMSK modulated signal is: 2 2( ) cos [ ( )] cos[ ( )] 2 2 nt b GMSK c k b t kb b b TE ES t t a g kT d t t T T T pω τ τ ω φ −∞ =−∞   = + − − = +    ∑∫ (6) E is the signal energy in the symbol period bT , )(tφ is the baseband phase, and the expression of baseband phase can be obtained from equation (6): ( ) [ ( )] 2 2 nt b k b kb T t a g kT d T pφ τ τ −∞ =−∞ = − −∑∫ (7) 3. Design Scheme of GMSK Frequency Hopping Modulation Normalizing the amplitude of GMSK modulated signal of equation (6) and obtaining the expression of the GMSK signal: cos[ ( ) ( )]GMSK cS t tω φ= + (8) The schematic diagram of GMSK frequency hopping modulation according to the above formula is shown in Figure 1. American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 31 Signal Preprocess Filter Integrator Cosine Operation Frequency-hopping Carriers Generator Input d(n) na ( )tφ Output ctω ( )ct tω φ+ Figure 1: The schematic diagram of GMSK frequency hopping modulation The working process is that the user inputs the code elements of the sequence combination of {0, 1}, then the code elements is preprocessed to obtain the bipolar non-return to zero code na , next the preprocessed na is filtered by the Gaussian low-pass filter, and through the integrator obtains the accumulated phase )(tφ of the waveform. Then sums the accumulated phase and the phase )(tcω generated by the frequency hopping carrier to obtain a total phase, and the total phase calculates the cosine values through the CORDIC operator, thereby the GMSK modulation of the input signal can be realized. 4. Implementation of GMSK Frequency Hopping Modulation on FPGA According to the Figure 1, the GMSK frequency hopping modulation can be divided into three parts: the frequency hopping module for generating the frequency hopping carrier phase, the phase accumulator for calculating the accumulated phase, and the CORDIC operator for phase cosine values, so the design of this scheme mainly discusses the FPGA implementation from these three parts. The FPGA implementation principle of GMSK frequency hopping modulation is shown in Figure 2. Input OutputPhase Accumulator Frequency-hopping Module )(tφ )()( ttc φω + )(tcω CORDIC Arithmetic Unit Figure 2: The FPGA implementation principle of GMSK frequency hopping modulation 4.1 Design of Frequency Hopping Module The frequency hopping module is composed of a PN code generator and a DDS frequency synthesizer. The PN code generator can generate pseudo-random hopping code elements, and different code elements are input to the DDS frequency synthesizer as different frequency control words, controlling the DDS exports the phase information of the sine wave, the cosine wave and the phase information of waveform. The principle of the frequency hopping module is shown in Figure 3. http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/javascript:showjdsw('jd_t','j_') American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 32 PN-code Generator DDS Frequency Synthesizer Frequency Control Word Frequency-hopping Carriers Figure 3: The principle of the frequency hopping module The PN code is generated by the m-sequence, and the primitive polynomial corresponding to m-sequence is set to . This is an m-sequence of order 4 and period of 15, so that 15 different pseudo-random codes can be generated, corresponding to 15 hopping points. The initial state of m-sequence is set to 0001, and the 15 pseudo-random codes generated according to the law of the m-sequence are {0001, 1000, 0100, 0010, 1001, 1100, 0110, 1011, 0101, 1010, 1101, 1110, 1111, 0111, 0011}, eventually jump back to 0001, 15 pseudo-random codes are 15 hopping points, cyclic jump according to this rule. When the frequency hopping carrier is generated by pseudo random codes, the output waveform frequency outf of the DDS frequency synthesizer and the input system clock clkf , the frequency control word K, and the data bit width N of the phase accumulator in the DDS have the relationship of the following equation (9) [6]: (9) The frequency resolution f∆ of DDS is: (10) The system index is 50MHz for intermediate frequency, 20MHz for bandwidth, and 400MHz for DDS input clock. In order to make the frequency hopping points fill the bandwidth as much as possible and meet the requirements of system specifications, the data bit width N of the phase accumulator is designed to 8 bits, and the frequency control word K is set to [25, 39], input the generated pseudo-random codes as the frequency control word K, 15 frequency control words corresponding to the DDS to generate 15 different frequency carriers, according to the formula (10), the frequency hopping interval, that is of the DDS is 1.5625MHz, so the 15 hopping points generated are 39.0625M, 40.625M, 42.1875M, 43.75M, 45.3125M, 46.875M, 48.4375M, 50M, 51.5625M, 53.125M, 54.6875M, 56.25M, 57.8125. M, 59.375M, 60.9375M, 15 frequency hopping points generate frequency hopping carrier according to the law of pseudo random codes. 4.2 Design of Phase Accumulator Module The code elements input by the user terminal can be processed by phase accumulator to obtain the accumulated phase )(tφ of the signal. The phase accumulation process is mainly to perform integral operations of the input signal waveform. 1)( 4 ++= xxxf N clk out Kff 2 × = N clkff 2 =∆ f∆ http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 33 The scheme sets the code element rate to 1 Mbps, and the sampling rate takes 50 times of the code element rate, that is 50 Mbps, which means that the signal is sampled 50 times in one symbol period. The input of the phase accumulator is the code elements of {0, 1}, and the calculation process of accumulated phase is shown in Figure 4. Figure 4: Calculation process of the accumulated phase Since the ideal Gaussian impulse response g(t) is infinitely long, it is unrealizable in physics, and the energy of g(t) is concentrated only in a limited interval, so we can truncate it in actual calculation [7], according to the waveform characteristic intercepts the length of bT5 , so the truncated )(tgT satisfies the following formula: - ( )T bg t dt T ∞ ∞ =∫ (11) The curve in Figure 4 is the Gaussian impulse response of the rectangular pulse corresponding to the code elements 732 ......aaa 、 . The truncation of bT5 is expressed as )2/( bdT TnTtg −− . By accumulative phase )(tφ expressed in the equation (7), the computational process of accumulative phase is as follows: 1 ( 1) ( 1) 0 ( ) ( ) ( ) 2 2 2 2 b b k k T tb b n T b k T bk T nb b T T t a g nT d a g kT d T T p pφ τ τ τ τ − − −∞ − = = − − + − −∑ ∫ ∫ (12) When bTt ≤≤0 ， 2( ) ( 2 ) 02 2 b T b d t T t a g T d T pφ τ τ= − −∫ (13) When bb TtT 2≤≤ ， 2 3( ) ( 2 ) + ( 3 ) 02 2 2 2 b b T b T b bd d tt T T t a g T d a g T d TT T p pφ τ τ τ τ= − − − −∫ ∫ (14) When bb TtT 32 ≤≤ ， 0 bT 2 bT 3 bT 4 bT 5 bT 6 bT 7 bT 8 bT 2a 3a 4a 5a 6a 7a http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 34 2 3 4( ) ( 2 ) + ( 3 ) + ( 4 ) 202 2 2 2 2 2 b b b T b T b T b b bd d d t tt T T T t a g T d a g T d a g T d T TT T T p p pφ τ τ τ τ τ τ= − − − − − −∫ ∫ ∫ (15) And so on, because ∫ = bTdttg )( , so when bb TntnT )1( +≤≤ ， 2 2 +1 2 2 ( ) ( 2 ) + ( ) 02 2 2 2 = ( ( 1) ) ( ( 2) ) ( 2)2 2 2 2 2 b b T b n T b bd d k b b n n T b n T b b bd d tt T T t a g T d a g nT d nTT T t tT T a a g n T d a g n T d n T nTT T p pφ τ τ τ τ p p pτ τ τ τ − + = − − + − − + + − + − + − + − − ∫ ∫ ∑ ∫ ∫ L L (16) It can be obtained from the above calculation process that the accumulative phase is divided into two parts, the instantaneous phase generated by the last five code elements and the accumulative phase of each symbol input before the last five symbols, the value of the accumulative phase is finally constant to π/2± . Every time you enter a new code element, the calculation is performed according to the above calculation process. Except for the last five code elements entered, the integral value corresponding to the previous code elements is 2/p , to calculate the integral, simply multiply the corresponding symbol value by 2/p and then sum. For the last five code elements, the sampling frequency of 50MHz corresponds to 50 sampling points for each symbol, and a bT5 truncated Gaussian impulse response corresponds to 250 sampling points, so 250 integral values can be generated, and the integral value is calculated as shown in the following equation (17). 0 1_ ( ) ( ) 2 t T b J g t g d T τ τ= ∫ (17) In MATLAB, evenly take 250 points to calculate the integral value, and store it in the register of FPGA for calling. When there is code element input, the code element is processed into NRZ code first, according to calculation formula of the accumulative phase (16), the last five NRZ codes as a group multiply the Gaussian integral values in the register then added to calculate the phase value, plus the accumulation of phase values of the code elements before the last five code elements, the sum of accumulated phase can be obtained, this value is the scale value of p , which is p/1 of the actual phase value. 4.3 Design of CORDIC Arithmetic Unit CORDIC is a method of numerical approximation by a finite number of iterative operations. It uses a series of yaws of angle associated with the operation base to approximate the angle of the rotation required [8]. It performs a plane rotation, the vector ( )ii YX , is transformed into the vector ( )jj YX , by the rotation . The angle of rotation θ can be obtained by a finite number of iterative calculations, and each iteration is as follows: 1 1 cos -sin sin cos n n n n n n n n X X Y Y θ θ θ θ + +       =            (18) http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element http://dict.cnki.net/dict_result.aspx?searchword=%e7%a0%81%e5%85%83&tjType=sentence&style=&t=code+element American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 35 When calculating the sine and cosine of the angle by the CORDIC algorithm, the initial vector ( )00 , yx is set to (1, 0), and the sine and cosine values of the phase angle can be obtained by using the CORDIC algorithm to find the vector ( )nn yx , with a rotation angle of θ . In the FPGA implementation of this scheme, since the input angle of rotation exceeds the operation range of [ ]pp，− of the CORDIC algorithm, so a CORDIC arithmetic unit structure with extended phase operation range is designed, which can perform CORDIC operation at any angle without being limited by the quadrant, the structure of this arithmetic unit is shown in Figure 5. Preprocessor CORDIC Core Processor Post Processor Input Output Figure 5: CORDIC arithmetic unit structure with extended phase operation The pre-processor inputs a phase signal with a scale of p . According to the periodicity of the trigonometric function, the value is first converted to the value in the interval [0, 2] by 2 cycles, and then the first phase of the binary phase is detected. If it is 0 means that in [0, 1] interval, that is the first and second quadrants. If it is 1 means that in [1, 2] interval, that is in the three or four quadrants. Signing which the quadrant is located, then send the data to CORDIC core processor to calculate the cosine value, and then the result is processed according to the flag bit to the corresponding quadrant to obtain the final cosine value. 5. Simulation and results The modulation scheme is simulated in MATLAB, taking the intermediate frequency 50MHz, the bandwidth is 20MHz, the frequency hopping points are 15. Select 20 input symbols d = [1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0], and the simulation result of the phase accumulator module is shown in Figure 6. In the figure, when the input symbol is 1, the output phase is increased, and when the input symbol is 0, the output phase is decreased, we can conclude that the phase information corresponding to the input symbol is generated by the operation of the phase accumulator module. Figure 6: MATLAB simulation diagram of phase accumulator module The overall simulation result of the system is shown in Figure 7. It can be seen that the modulation of the American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 36 present scheme generates a GMSK modulated signal of carrier hopping corresponding to the input code elements. Figure 7: MATLAB simulation diagram of GMSK modulation To further verify the correctness of the overall scheme, the design is implemented on the ISE platform of the FPGA, then the whole system is simulated and verified by Modelsim software. The result is shown in Figure 8 below. The input data din is the code elements sequence of {0, 1} combination. It can be seen that the value of the phase gmsk_phase output by the phase accumulator is continuous, and when the input data din is 1, the value of gmsk_phase increases, when din is 0, the value of gmsk_phase decreases. It is consistent with the waveform of the phase in the MATLAB simulation, which proves the correctness of the FPGA implementation of the scheme. Phase_out is the phase information of the frequency hopping carrier generated by the frequency hopping module. The gmsk_phase of the output of the phase accumulator is added to the phase hop signal phase_out of the frequency hopping generated by the frequency hopping module to obtain the phase sum_phase, and then the CORDIC operation is performed to get the cosine value, and the GMSK modulation signal gmsk is generated, finally implements GMSK modulation of carrier frequency hopping for the input data. Figure 8: Simulation diagram of GMSK modulation American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 37 The above results show that the GMSK frequency hopping modulation method proposed in this paper realizes the frequency hopping function of GMSK carrier, ensures the phase continuity of modulated signal, and saves a lot of complicated multiplication operations, which makes the realization of frequency hopping communication system simpler. 6. Conclusion In this paper, an FPGA-based GMSK frequency hopping modulation scheme is designed. The frequency hopping module is added to the GMSK modulation system to realize the control of frequency hopping. The design of phase accumulator and CORDIC algorithm simplify the modulation scheme, which not only ensures the continuity of the phase but also saves a lot of multiplication operations,it also improves the feasibility of the scheme and saves a lot of storage space of the system. The scheme is implemented in the Verilog HDL language on the Xilinx ISE software and simulated on Modelsim software. The simulation results show the correctness and feasibility of this scheme. References [1] Wu X, Shi J H. Anti-Interference Performance Analysis in Bluetooth Frequency Hopping System[C]. IEEE International Workshop on Anti-Counterfeiting, Security, Identification. IEEE, 2007: 328-331. [2] Popovski P, Yomo H, Prasad R. Dynamic adaptive frequency hopping for mutually interfering wireless personal area networks[J]. IEEE Transactions on Mobile Computing, 2006, 5(8): 991-1003. [3] Iqbal R, Akhtar M W, Junaid M, et al. A design framework for frequency hopped communication system[C]. Proceedings of 2016 13th International Bhurban Conference on Applied Sciences and Technology, IBCAST, 2016, 9: 699-703. [4] De-Xin L I, Gao X J, Zhuang Z. Design for GMSK frequency-hopping communication system based on Simulink[J]. Journal of Jilin University (Information Science Edition), 2007, 25(4): 391-7. [5] Babu K M N, Vinaymurthi K K. GMSK modulator for GSM system, an economical implementation on FPGA[C]. International Conference on Communications and Signal Processing. IEEE, 2011: 208-212. [6] Huang C, Ren L X, Mao E K, et al. A systematic frequency planning method in Direct Digital Synthesizer (DDS) design[C]. International Conference on Wireless Communications and Signal Processing. IEEE, 2009: 1375-1378. American Scientific Research Journal for Engineering, Technology, and Sciences (ASRJETS) (2018) Volume 47, No 1, pp 28-38 38 [7] Peng W J, Song W T, Luo H W. Application and performance analysis of GMSK modulation in frequency-hopping communication[J]. Journal of China Institute of Communications, 2000, 21(11): 41-47. [8] Liu X Y, Liang X M. Theory and Implementation of GMSK Tamed Spread Spectrum Modulation Technology[J]. China Academy of Electronics and Information Technology, China, 2010, 5(4): 415-418. 3. Design Scheme of GMSK Frequency Hopping Modulation 4. Implementation of GMSK Frequency Hopping Modulation on FPGA 4.1 Design of Frequency Hopping Module 4.2 Design of Phase Accumulator Module 4.3 Design of CORDIC Arithmetic Unit 5. Simulation and results 6. Conclusion