id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
can-6236	Vittapu, Sravan K.; Sankuru, Ravichand; Bolimera, Ravi; Ramudu, Kuruva Madhu; Reddy, Mekala Rameshwar; Reddy, Maddula Manasa	Reversible logic-based parity generator circuit for nano communication network using QCA	2024	11	.pdf	application/pdf	3894	282	57	Reversible circuit design has generally received far more attention in recent decades [13]; the Feynman gate is one of the most well-known reversible arithmetic logic gates. This study proposes an optimised reversible Feynman design implementation using parity generators, parity checker gates, and the efficient XOR proposed by Ahmed and Naz	cache/can-6236.pdf	txt/can-6236.txt