id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
cana-3341	T.Swapna Rani	Design and Analysis of High Speed Low Power 4T-2R finFET-Memristor based SRAM	2025	11	.pdf	application/pdf	4522	307	54	SRAM cell data indicates that R1 or R2 is set for low-level reading and writing. CTRL2 is VDD during RESET, whereas R1 or R2 is HRS depending on SRAM cell data.	cache/cana-3341.pdf	txt/cana-3341.txt