id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
cana-4854	T. Jayachandra Prasad	Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process	2025	14	.pdf	application/pdf	3622	231	66	The suggested adder, for instance, yields a PDP of 23.798 fJ for 4-digit operands, whereas other efforts yield 41.364 fJ, 31.137 fJ, 32.376 fJ, 49.059 fJ, and 49.882 fJ. Keywords: — BCD arithmetic units, Complementary MOS, CLA (Carry Look-ahead Adder) 1. BCD arithmetic units provide accurate decimal calculations with four-bit codes [9], [11].	cache/cana-4854.pdf	txt/cana-4854.txt