id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
cana-5231	D. Satyanarayana	Design of Efficient Multiplier with Low Power and High-Speed Using PTL (Pass Transistor Logic)	2025	10	.pdf	application/pdf	2912	175	55	Though the integration of PTL FA further lowers circuit power, this could increase the critical path delay a little bit. Further- more, cascading PTL circuits cause large delays, as observed in [10].	cache/cana-5231.pdf	txt/cana-5231.txt