id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
cana-5248	S. Govindarajulu	Implementation of Fast, Power and Energy Efficient CMOS Flip-Flops in 45 Nm Regime	2025	12	.pdf	application/pdf	4035	194	51	Keywords: Asynchronous Reset, CMOS technology, dual edge triggering,Energy efficiency, flip flops, low power, Power Delay Product (PDP), Single-Phase Clocked (SPC). [7] C.K.Teh, M.Hamada, T.Fujita, H.Hara, N.Ikumi and Y.oowaki, “Conditional data mapping flip-flops for low power and high performance systems,” IEEE Trans.	cache/cana-5248.pdf	txt/cana-5248.txt