Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 971 https://internationalpubls.com Low-Power DSP Architectures for Wireless Communication Using Vedic Mathematics Ramesh Solanki1, Dr.Mahesh Jariya2 1Research Scholar, Children's Research University,Gandhinagar-382021,Gujarat (India) rameshsolanki_maths12@yahoo.com 2Associate professor, Saurashtra University, Rajkot-360005, Gujarat (India) mahesh.jariya@gmail.com Article History: Received: 12-09-2024 Revised: 22-10-2024 Accepted: 01-11-2024 Abstract: In this research work, a Vedic mathematics-based computation technique has been used to explore low-power DSP architectures for wireless communication. Finally, Urdhva Tiryagbhyam, Nikhilam, and Paravartya algorithms are studied in this thesis and the results indicate that these algorithms use less energy, take less time to execute, less time taking and fast algorithm. Statistical modelling, clustering and machine learning-based prediction are performed for performance analysis. Results show that optimized DSP architectures offer a very significant improvement in signal processing efficiency, and thus, are very appropriate for input/output (IoT), 5G and embedded systems. Therefore, the study proposes the integration of Vedic-based DSP in high-performance low-power wireless communication solutions. Keywords: Low Power DSP Architecture, Vedic Mathematics, Bit Error Rate, Nikhilam Sutra, Machine Learning, Wireless Communication, K-means Clustering, Linear Regression, FIR, IIR, LMS, Throughput, Paravartya. I. INTRODUCTION Background of The Research In modern wireless communication systems, DSP architectures in terms of efficiency, speed and accuracy are highly important, and having low power is good. However, traditional DSPs consume a lot of power and cannot meet the requirements of the applications including the IoT, mobile communication and biomedical signal processing systems [1]. Since there exist Vedic Mathematics-based DSP architectures that promise to contribute to high computational efficiency with low power consumption, these architectures show promise to overcome these limitations. Such techniques are of the form of Urdhva Tiryagbhyam, Nikhilam and Paravartya algorithms used in an ancient Indian mathematical system known as Vedic mathematics for faster multiplication and arithmetic operations. These techniques provide a replacement for traditional multidimensional signal processing architecture using less number of logic operations and less processing delay [2]. When integrated with mailto:rameshsolanki_maths12@yahoo.com mailto:mahesh.jariya@gmail.com Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 972 https://internationalpubls.com DSP units, Vedic Mathematics generates excellent throughput, energy efficiency and signal processing performance with high accuracy. On the other hand, in this research, a DSP architecture is designed and the performance of low-power DSP architectures which use Vedic multipliers for wireless communication applications is analyzed [5]. In this study, the feasibility of energy-efficient DSP solutions is investigated to reduce power consumption by varying the performance of wireless networks from signal-to-noise ratio, bit error rate, and performance, to area utilization. Aim and Objectives Aim This research aims to develop and evaluate low-power DSPs suitable for wireless communications using Vedic Mathematics computation schemes to minimize energy consumption, power saving and processing speed with high accuracy of signal for energy-constrained wireless systems [3]. Objectives ● To develop a low-power Vedic mathematics-based DSP architecture for wireless communication systems. ● To evaluate and compare the power consumption, energy efficiency and speed of Vedic-based DSP units with respect to the conventional architectures. ● To determine the quality of signal, latency and bit error rate of wireless transmission. ● To improve DSP’s performance on-energy-restricted application such as IoT and mobile communications. ● To predict the DSP efficiency and its performance improvement with machine learning-based predictive analysis that is taken up to perform. Rationale High-speed, energy-efficient DSP architectures are needed to realize efficient signal processing with minimum power consumption for wireless communication systems [4]. New approaches in this area of using DSP architectures based on Vedic Mathematics to improve the efficiency of computation, reduce latency, and increase energy efficiency make them applicable to IoT, mobile networks, low power power- embedded systems applications. II. LITERATURE REVIEW 1. Vedic Mathematics in DSP Architectures The use of an ancient Indian mathematical system, Vedic mathematics, has attracted the attention of digital signal processing (DSP) because of its flexibility in arithmetic computation. Urdhva Tiryagbhyam, Nikhilam and Paravartya are key algorithms which provide a systematic way to do high speed Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 973 https://internationalpubls.com multiplication and arithmetic operations with very little increase in processing overhead. In comparison to the conventional multiplication methods like Booth and Array multipliers, Vedic multipliers need the least number of logic gates, making Vedic multipliers more suitable with respect to hardware complexity and energy consumption [6]. High speed and low power DSP architectures can be studied using Urdhva Tiryagbhyam multiplication (vertical & crosswise multiplication) based on the studies, and it is seen that this multiplication is highly suitable for the above described architectures. However, FPGA based implementations of Vedic DSP architectures have yielded significant speed up, power efficiency and utilisation of area. In addition, the utilization of Vedic algorithms results in enhanced pipelining and increased parallel processing, such as the ability available in a DSP unit, making them the best fit for the real-time wireless communication applications like the IoT, biomedical signal processing and the mobile communication networks where low latency and accuracy are necessary. 2. Low-Power DSP Architectures for Wireless Communication Due to the emerging applications in wireless communication systems, modern wireless communication systems need to offer energy efficient DSP architectures that carry out real time signal processing with low power consumption. The amount of arithmetic operations as well as the data processing routines that conventional DSP units (such as MAC (Multiply Accumulate) units and FFT processors) involve, makes their power consumption large. Efforts have been made to reduce the DSP power by means of power and clock gating as well as adaptive voltage scaling, all of which constitute low power design techniques [7]. But Vedic based DSP architectures offer an alternative in lower power dissipation due to reducing a number of logic operations. Vedic multipliers have been shown to be implemented both with power efficiency and processing speed improvements in DSP filters, convolution operations, and error correction algorithms. With capabilities to extend the battery life whilst real-time data processing, these architectures are very useful for battery-powered applications in mobile networks, IoT edge devices, and biomedical signal processing [8]. This work explores emerging energy efficient DSP designs using Vedic-based multipliers in next generation wireless networks by replacing conventional multipliers. 3. Performance Metrics: Power, Latency, and Bit Error Rate (BER) Metrics including the power consumption, processing delay (latency), bit error rate (BER) and area utilization are often the primary assessment measures of the efficiency of DSP architectures in wireless communication. Highly accurate conventional DSP architectures, however, result in high power consumption and high propagation delays that render their use unattractive in energy-constrained applications [9]. It has been shown through the research that the power dissipation and computational speed of Vedic Based DSP architectures is lower than that of the conventional Booth, Wallace and Karatsuba multipliers. As demonstrated by comparing Urdhva Tiryagbhyam and Nikhilam based multipliers, it was found that Vedic algorithms shortens critical path delay and dynamic power consumption while giving better performance in real time wireless transmission. Optimizing the signal to noise ratio (SNR) and minimizing BER are also important for having robust wireless communication. In DSP units, where the Vedic multipliers are integrated, better BER (bit error rate) and better signal integrity Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 974 https://internationalpubls.com properties can be obtained, and make the Vedic multipliers an ideal choice for error correction, modulation, and filtering schemes. 4. Machine Learning for DSP Performance Optimization Recently, machine learning (ML) models have been integrated within DSP architectures to enable power predictions and optimization of power consumption, latency, computational efficiency in wireless communication systems. Traditional DSP optimisation techniques are based on static hardware configurations, which may not optimally adapt to the changing signal conditions. However, ML-based approaches make real-time data analysis and predictive modelling for dynamic adjustment of DSP parameters in an optimal manner [10]. It has been shown that regression models, decision trees and neural network models can be used to forecast energy consumption, processing speed and error rates from past DSP performance data. Adaptive power management & processing speed can be achieved by training ML models on signal characteristics, noise levels and computational load in order to solve the problem in a power-constrained environment. Implementing ML driven DSP optimization in IoT, 5G, and Mobile networks can reduce power wastage, improve overall wireless system reliability and efficiency, and increase the precision of signal processing by orders of magnitude. Literature Gap Though there has been significant progress in low power DSP architectures and incorporating Vedic Mathematics for high speed arithmetic operations, still many research gaps have remained open. Instead, most of the existing studies are in the context of individual multiplier efficiency, not an overall DSP architecture that provides enhanced wireless communication. Vedic multipliers like Urdhva Tiryagbhyam and Nikhilam have already helped in reducing power consumption and latency, but the potential impact of these on bit error rate (BER), signal integrity and adaptive processing in dynamic wireless environments remains unexplored [11]. Additionally, real-time DSP configurations for energy efficiency through the integration of ML for predictive DSP optimization is still in its infancy, and there is little exploration of adaptive DSP configurations for energy efficiency. Additionally, comparative studies to assess the DSP performance of Vedic architecture using modern low power architectures like approximate computing and neuromorphic DSP are not available. These gaps are addressed, which will lead to the development of fully optimized, energy efficient DSP architectures for next generation wireless systems. III. METHODOLOGY Research Approach The present research is a quantitative and analytical approach to evaluating the performance of wireless communication using the low-power DSP architecture, which is developed using the scheme of Vedic Mathematics. This study has engaged in data collecting, algorithm implementation & performance evaluation process [12]. Vedic multipliers such as Urdhva Tiryagbhyam, Nikhillam and Paravartya algorithms are implemented and integrated into DSP architectures. Real-world and synthetic datasets are Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 975 https://internationalpubls.com used to analyze the efficiency, power consumption, and computational speed. Predictions are made of DSP performance trends using machine learning models [13]. This tool based on the fact that the desired trade-offs exist between latencies, processing accuracy, and energy efficiency is statistically analyzed and visualized using techniques of clustering and regression to identify the optimal trade-offs. Research Design In this study, an experimental and computational research design has been used to develop and test low- power DSP architectures which use Vedic Mathematics-based computation techniques for wireless communication. The effort is made to design, simulate and analyze DSP units with Vedic multipliers that increase energy efficiency, processing speed and signal accuracy [14]. Having selected Vedic multiplication techniques, i.e. Urdhva Tiryagbhyam, Nikhilam and Paravartya algorithms, the work proceeds with their implementation in digital hardware simulations. The performance parameters of power consumption, area utilization and latency are measured in these architectures modelled in Python-based signal processing libraries. The experimental design is such that it is ensured that Vedic-based DSP architectures are benchmarked against the conventional multiplication methods implemented in DSP systems. Fig. 1: DSP Architecture Design Flowchart with Vedic Mathematics Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 976 https://internationalpubls.com In addition to the overall research, machine learning-based predictive modelling is used in describing trends and performances of the DSPs. In regression and clustering techniques, the DSP architectures are classified based on efficiency, signal quality and computational overhead [15]. Also, algorithmic optimizations to minimize the power consumption as much as possible without oversizing the power supply to sacrifice computational accuracy are considered. Real-world wireless communication scenarios are simulated to verify the proposed architectures and to determine SNR, BER and throughput. The research becomes easy to get along with if it is carried out through a methodology, and therefore the results are more repeatable and accurate in terms of performance evaluation. The research findings are then systematically interpreted and design recommendations for the energy-efficient DSP architectures that are commonly used in IoT devices, mobile networks and also embedded systems where power efficiency matters are presented. Data Analysis and Collection The research analyzes the effectiveness of Vedic Mathematics proposed DSP architectures in terms of secondary datasets and simulated data associated with wireless communications. DSP performance metrics are included such as clock frequency, Power Consumption, Latency, Area Usage, SNR, BER, throughput, and so on. The data used in these datasets come from published research papers, industry benchmarks, as well as experimental simulations with Python-based signal processing tools. Statistical techniques and machine learning models are applied to identify trends, correlations, and performance trade-offs for the data analysis. Power efficiency is summarized by descriptive statistics and DSP performance is predicted by regression analysis under varying conditions [16]. That is, K means clustering segment architectures based on energy efficiency and computational speed. Furthermore, visualization for DSP design trade-offs takes the form of scatter plots, box plots, heatmaps, etc. Interpretation of the results for use in optimizing low-power DSP architectures for application in energy- constrained applications such as IoT and Mobile networks. Tools/Techniques to be Used Python-based computational tools and machine learning techniques are used in this research for designing, analyzing and optimizing low-power DSP architecture using Vedic Mathematics for wireless communication. For the implementation of signal processing algorithms, NumPy and SciPy are used, whereas pandas come in handy for the preprocessing of data [17]. Visualizing the DSP performance metrics such as power consumption, latency and the accuracy of the signal is done with the help of Seaborn and Matplotlib. Once again, machine learning based on predictive modelling using regression analysis, and clustering (KMeans) is applied and feature selection is performed to optimize DSP configurations using Scikit Learn [18]. FIR and IIR filter design methods are implemented to evaluate signal quality improvements using digital filter design techniques. Further, this work also investigates the effect of Vedic-based DSP computation on the signal transmission efficiency through FFT-based spectral analysis. Vedic-based DSP architectures are benchmarked to show how data-driven approaches are used to get the Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 977 https://internationalpubls.com best in terms of energy efficiency, computational speed and reliability of wireless communication applications. Ethical Considerations By design and evaluation of low-power DSP architectures, is an effort to follow ethical guidelines such as data integrity and accuracy as well as transparency. The datasets used in all cases are publicly available, and industry-standard benchmarks or simulations are generated to ensure that the datasets used are adherent to data privacy regulations [19]. The analysis does not include any personally identifiable information (PII). Like fair and unbiased algorithmic evaluation, the study does not attempt to use data manipulation or misrepresent any results. Finally, the existing research and computational models are accurately cited and acknowledged to promote academic integrity. The research findings are unbiased and are responsibly deployed for the advancement of wireless communication. IV. RESULTS AND DISCUSSION Fig. 2: Vedic Multiplication The computational efficiency, of Vedic Multiplication using Urdhva Tiryagbhyam Sutra for the DSP application is shown in this figure. It provides an energy-saving and processing speedway and is suitable for low-power wireless communication. It has the advantage of reducing the arithmetic complexity while improving latency as well as power efficiency greatly for high-speed digital signal processing in embedded communication systems. Fig. 3: FIR Filter Design for Low-Power Architecture The Finite Impulse Response (FIR) filter is designed using a Hamming window and is suitable for low- power DSP architectures, in the figure. However, this filter is optimized to remove unwanted high- Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 978 https://internationalpubls.com frequency noise with very little disruption to the signal. Although it is suited for wireless communication and real-time signal processing applications, the optimized coefficients improve energy efficiency power reduction, and system stability. Fig. 4: IIR Lowpass Filter Design This is an infinite impulse response (IIR) Butterworth low pass filter that’s fundamental to wireless signal processing. It provides high signal fidelity under high-frequency noise and low power consumption. It is highly effective for real-time, low-power wireless communications applications and noise reduction algorithms because the filter coefficients are optimized to have a smooth frequency response. Fig. 5: BPSK Modulation and Demodulation The scheme in the figure is Binary Phase Shift Keying (BPSK) modulation and demodulation, which is a quite popular digital modulation scheme [20]. For wireless channels, binary data is well encoded by BPSK. This demodulation process properly recovers transmitted bits while at the same time reducing bit error rates (BER), meaning that the reliability is high, power efficiency, and signal integrity, are improved in wireless communication systems such as IoT and mobile networks. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 979 https://internationalpubls.com Fig. 6: Low-Power Vedic-based MAC Unit This figure illustrates a Vedic multiplier-based MAC unit to enhance the computational speed and energy efficiency. Based on the design, the latency, power consumption and area utilization (AUC) of DSPs are reduced. It significantly improves real-time processing capabilities, thus, it is a high-performance, low- power wireless communication, digital filtering, and fast arithmetic computation solution for embedded processing units. Fig. 7: FFT Magnitude Spectrum In applications of DS, spectrum analysis of the signals is performed by the Fast Fourier Transform (FFT) magnitude spectrum. The figure shows that frequency domain transformation is required for wireless signal processing and modulation analysis [21]. With such an implementation, optimized power efficiency, lower computational complexity and better frequency resolution can be achieved, and therefore, it is appealing for low-power spectrum sensing, wireless data transmission and real-time communication systems. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 980 https://internationalpubls.com Fig. 8: Convolution of Signal Using Vedic Mathematics In this figure, Vedic multiplication is carried out to facilitate efficient real-time digital filtering in DSP applications using convolution. The approach achieves this with little computational and processing time and energy usage and without loss of signal accuracy. In addition, for wireless communication, it is optimized to enhance filtering performance, power consumption and quality of signal, thus, it is a good technique for the application of adaptive filtering and embedded DSP architecture. Fig. 9: Adaptive Noise Cancellation Using LMS Algorithm The Least Mean Squares (LMS) adaptive filtering technique for adjusting the filter weights dynamically to achieve wireless communication with the least noise is illustrated in this figure. It also improves noise suppression efficiency, minimizes power consumption and gives crisp signals [22]. There is an adaptive learning technique that allows the technique to optimise wireless transmission quality for real-time applications, such as speech enhancement and mobile networks, whilst ensuring low-power DSP architectures are adaptive learning. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 981 https://internationalpubls.com Fig. 10: Distribution of Signal Energy Signal energy distribution as in this histogram is of great importance to spectrum sensing and cognitive radio. It also assists in detecting free spectrum bands for wireless transmission efficiency. The visualization allows efficient power allocation, consumption of low power, and provision of excellent communication performance while dynamic spectrum access, signal classification, and energy-efficient wireless network management in a real-time DSP environment. Fig. 11: Statistical Summary of The DSP Design Data The statistical insights provided by this figure are based on over 200 DSP designs discussed here and analyze key parameters such as clock frequency, power consumption, area usage, latency, SNR, BER, throughput and energy efficiency. It provides a quantitative firm ground for analyzing the performance Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 982 https://internationalpubls.com and energy optimality of Vedic Mathematics-based DSP architectures for wireless communication systems. Fig. 12: Power Consumption vs Clock Frequency In this scatter plot, the power consumption is plotted with regard to clock frequency for various Vedic Multiplication Algorithms implemented in DSP designs [23]. Such a plot helps to identify low-power, high-frequency DSP architectures that are power-efficient for wireless communication applications, such as IoT, Mobile networks and embedded signal processing systems. Fig. 13: Energy Efficiency by Vedic Algorithm Type This box plot compares energy efficiency (pJ/op) across Paravartya, Urdhva Tiryagbhyam, and Nikhilam algorithms. Analysis of the variation shows that the power consumption and computational effectiveness of the wireless communication match with Paravartya DSP architecture is an optimum electrically efficient signal processing. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 983 https://internationalpubls.com Fig. 14: K-Means Clustering of DSP Performance This figure categorizes DSPs by DSP architectures through KMeans clustering to group designs by clock frequency and power consumption. The clustering analysis reveals DSP performance classes and is thus useful to determine appropriate algorithms for low-powered wireless communication applications concerning a suitable tradeoff between computational efficiency and energy savings. Fig. 15: Power Consumption by Vedic Algorithm Type The power consumption across several Vedic multipliers utilized for DSP designs is shown in this box plot. Comparison is made between algorithms to select which one minimizes power dissipation, necessary in designing energy-efficient DSP architectures for wireless communication, embedded systems or signal processing applications [24]. Thus, Paravartya is the best algorithm consuming the least power for the DSP architecture. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 984 https://internationalpubls.com Fig. 16: Optimal Design of DSP Architecture Using Urdhva Tiryagbhyam Algorithm In this figure, the best-performing DSP is shown with the Urdhva Tiryagbhyam multiplier for having minimum energy consumption, maximum throughput, and minimum latency. This architecture is found to be a Vedic-based architecture with enhanced computational speed without losing energy efficiency and this analysis confirms that such architecture is well suited for real-time wireless signal processing. Fig. 17: Optimal Design of DSP Architecture Using Nikhilam Algorithm The figure represents the best DSP Design with the Nikhilam multiplication technique which offers good energy efficiency, lower bit error rate and faster processing. With this design particularly suited for low- power embedded DSP applications, e.g. mobile networks and IoT-based wireless communication, the implementation of the design and simulations are presented afterwards. Fig. 18: Predicted DSP Performance with Linear Regression Model Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 985 https://internationalpubls.com The description regarding a machine learning-based regression model using the predicted vs. actual throughput of DSP designs is presented in this figure. These predictions of DSP performance are evaluated for accuracy to better optimize low-power DSP architectures for wireless applications with both improved computational efficiency and reduced overall power consumption. V. CONCLUSION Summary of Findings Wireless communication using Vedic Mathematics-based multiplication techniques is presented in this research and examined as to its performance on low-power DSP architectures. It is found that the algorithms of Urdhva Tiryagbhyam, Nikhilam and Paravartya have a great impact on reducing the latency, power consumption, and the area used by the conventional DSP architecture. It is statistically verified that the DSP designs based on Vedic Mathematics are more energy efficient and thus are fit for IoT, mobile networks, and real-time signal processing. However, it shows that there are distinct DSP performance categories that are efficiently selected to choose the energy-optimized architecture. A predictive model based on machine learning is developed to look exactly through the DSP throughput and achieve better resource allocation and performance optimization. In addition, improvements in signal-to-noise ratio (SNR) and bit error rate (BER) are achieved through filter designs such as FIR, IIR as well as Vedic multiplication with integrated wireless transmission reliability. Vedic-based DSP architecture is compared with the traditional method to show its high advantage over high-speed and low-power applications. The results show that computational accuracy and signal quality are not sacrificed when designing energy-efficient DSP solutions. These findings justify the applicability of DSP architectures based on Vedic Matrix, in future low-power wireless communication and embedded system systems to achieve sustainable and energy efficient as well as high-performance digital signal processing. Research Recommendation Based on these results, a Vedic Mathematics-based architecture is recommended to be integrated into the energy-efficient wireless communication systems to achieve computational speed and power efficiency. Thus, designers choose Urdhva Tiryagbhyam and Nikhilam which are given more preference over the implementation of Latency Reduction and throughput optimization [25]. To optimally design DSP parameters during predictive performance, machine learning models must be used for predictive performance analysis. This also can help in enhancing signal quality and reliability of transmission using adaptive filtering techniques. Vedic-based DSP solutions reach the industry and the development of sustainable, high-performance, low-power embedded systems happen for the next generation of wireless and IoT applications. Future Work Hardware implementation of the Vedic-based DSP architectures on FPGAs and ASICs is a topic of future research for real-world investigation. Methods of further enhancing computational efficiency include Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 986 https://internationalpubls.com improvements in parallel processing techniques. Further, combining AI-driven DSP optimization will also enable dynamic power adaptation and make these architectures more flexible for 5G, IoT, and real-time signal processing. VI. REFERENCES [1] Padma, C., Jagadamba, P. and Reddy, P.R., 2021. Design of FFT processor using low power Vedic multiplier for wireless communication. Computers & Electrical Engineering, 92, p.107178. [2] Velliangiri, A., Kalimuthu, V.K. and Balaji, C.G., 2025. IoT based Performance Improvement of Single Instruction Multiple Data (SIMD) Processor Array for Wireless Sensor Networks Application. Tehnički vjesnik, 32(1), pp.66-71. [3] Sridevi, A. and Sathiya, A., 2024. Design of energy efficient N-bit vedic multiplier for low power hardware architecture. International Journal of Electronics, pp.1-21. [4] Pasuluri, B.S. and Sonti, V.K., 2022, February. Reducing Computational Complexity in Digital Circuit Designing using Ancient Mathematics: A Review. In 2022 IEEE Delhi Section Conference (DELCON) (pp. 1-9). IEEE. [5] Prema, A. and Karthikeyan, A., 2024. Design and implementation in power-efficient and thermal conductivity of vedic processor for embedded applications. Thermal Science and Engineering Progress, 55, p.102895. [6] Khubnani, R., Sharma, T. and Subramanyam, C., 2022, March. Applications of Vedic multiplier-a review. In Journal of Physics: Conference Series (Vol. 2225, No. 1, p. 012003). IOP Publishing. [7] Kumar, A. and Agarwal, R.P., 2021. Design and implementation of efficient FIR low pass filters based on vedic and traditional digital multiplier algorithm. In Advances in Mechanical Engineering: Select Proceedings of CAMSE 2020 (pp. 271-279). Singapore: Springer Singapore. [8] Gavaskar, K., Malathi, D., Ravivarma, G., Devi, V.K., Megala, M. and Begam, S.M., 2022. A fresh design of power effective adapted vedic multiplier for modern digital signal processors. Wireless Personal Communications, 124(2), pp.1297-1315. [9] Sharma, N.K., Rathore, S. and Khan, M.R., 2021. A New Speed Power Area and Accuracy (SPAA) Aware Cordic Processing Unit By Vedic Mathematics For The Application of Computer Vision. Turkish Journal of Computer and Mathematics Education Vol, 12(2), pp.3199-3209. [10] Kishore, S., 2024. EFFICIENT 64-BIT VEDIC MULTIPLIER DESIGN FOR ENHANCED COMPUTATIONAL SPEED. International Journal of Advance Scientific Research, 4(11), pp.6-10. [11] Shanthi, K.G., Sandhiya, G., Abinaya, K., Sangeetha, A., Aruna, T. and Aswini, R., 2022, August. Performance analysis of vedic multiplier and modified vedic multiplier in direct digital synthesizer. In 2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC) (pp. 64-67). IEEE. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 987 https://internationalpubls.com [12] Dharani, S.M., Satheesan, M.A., Asuvanti, M.A., Kumar, R. and Vidhya, S., 2021, February. Design and analysis of high-speed low-power vedic multiplier with 3-1-1-2 compressor using reversible logic gates. In IOP Conference Series: Materials Science and Engineering (Vol. 1059, No. 1, p. 012024). IOP Publishing. [13] Pasuluri, B.S. and Sonti, V.K., 2021, May. Design of Vedic multiplierbased FIR filter for signal processing applications. In Journal of Physics: Conference Series (Vol. 1921, No. 1, p. 012047). IOP Publishing. [14] Giridaran, S., Ravindran, P.A., Raj, G.D. and Janarthanan, M., 2022. Design of Low Power Vedic Multiplier Using Adiabatic Techniques. In Cognitive Informatics and Soft Computing: Proceeding of CISC 2021 (pp. 403-415). Singapore: Springer Nature Singapore. [15] Patil, R.M., Manjunath, T.C. and Pavithra, G., 2024, December. Harnessing QCA for High- Performance, Low-Power Arithmetic Circuits: A Focus on Multipliers and Square Circuits. In 2024 4th International Conference on Mobile Networks and Wireless Communications (ICMNWC) (pp. 1- 8). IEEE. [16] Ahmadpour, S.S., Navimipour, N.J., Ain, N.U., Kerestecioglu, F., Yalcin, S., Avval, D.B. and Hosseinzadeh, M., 2024. Design and implementation of a nano-scale high-speed multiplier for signal processing applications. Nano Communication Networks, 41, p.100523. [17] Chugh, H. and Singh, S., 2023, July. Parametrical analysis and thermal sensitivity study of 8-bit vedic multiplier. In 2023 14th international conference on computing communication and networking technologies (ICCCNT) (pp. 1-6). IEEE. [18] Somineni, R.P., Kumar, A.S., Pedduri, J., Naidu, C.D., Sreenivasulu, V.B. and Neelam, A.K., 2023, December. An Efficient High Performance GDI based 4-bit Vedic Multiplier in 32nm Technology. In 2023 Global Conference on Information Technologies and Communications (GCITC) (pp. 1-6). IEEE. [19] Mendez, T. and Nayak, S.G., 2023, January. Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier. In 2023 International Conference for Advancement in Technology (ICONAT) (pp. 1-6). IEEE. [20] SANKAR, M.P.R., SATYANARAYANA, S., KUSUMA, I., SRIKANTA, K., RAJU, R. and VASANTHA, M., 2024. EFFICIENT IMPLEMENTATION OF 2, 4, 8 BIT MULTIPLIERSWITH “URDHAVA TRIYAKBHYAM” VEDIC ALGORITHM. International Journal of Engineering Research and Science & Technology, 20(1), pp.23-30. [21] Sharma, V.P., Patidar, H., Raut, G., Maheshwari, V. and Kar, R., 2023. Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology. e-Prime-Advances in Electrical Engineering, Electronics and Energy, 4, p.100157. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 31 No. 8s (2024) 988 https://internationalpubls.com [22] Alnuaimi, S.S., Yuvaraj, D., Noori, S.F. and Sudhakaran, P., 2023. Systematic Review on Multiply and Accumulate Unit (MAC) Architectures and Comparison with Various Multipliers. IIRJET, 9(2). [23] Sharanya, B., Kavitha, M.T. and Raju, Y.D.S., 2021. LOW AREA HIGH SPEED COMBINED MULTIPLIER USING MULTIPLEXER BASED FULL ADDER. INTERNATIONAL JOURNAL, 6(1). [24] Kumar, B.M. and Rangaraju, H.G., 2021. Array Multiplier and CIA based FIR Filter for DSP applications. International Research Journal on Advanced Science Hub, 3(1S), pp.52-59. [25] Senthilkumar, V.M., Nirmala, R., Kumar, R.S. and Kumar, K.V., 2025. Enhanced Low Power FinFET-Based Flash ADC Design for High-Speed Electronics Applications. Tehnički vjesnik, 32(2), pp.466-473.