Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3289 https://internationalpubls.com N-bit Multiplexers Using Verilog Ponnala Lakshmi Prasanna Seshadri Rao Gudlavalleru Engineering College, JNTUK Article History: Received: 01/01/2025 Revised: 06/02/2025 Accepted: 10/03/2025 Abstract Multiplexer is a digital circuit with multiple inputs and one output. It is a Multi input single output circuit. Multiplexers uses the notation 2n X 1 or 2n : 1 or 2n to 1. n represents select lines. The paper n-bit Multiplexers Using Verilog includes three Multiplexers 1-bit 8X1 Multiplexer, 8-bit 8X1 Multiplexer and 8-bit 16X1 Multiplexer. The three Multiplexers are designed, simulated and Synthesized Using Verilog. The Verilog Modules of each Multiplexer are developed and Synthesized to obtain RTL and Technology schematics. In the next step, The verilog Test benches are developed for each Multiplexer and simulated using Behavioral simulation to obtain the Output waveforms. Next The Output waveforms are verified as per the given Truth Tables. The design summary of each Multiplexer can be obtained after synthesization and simulation. The design summary includes Timing Summary, Device Utilization Summary, Primitive and Black Box Usage and Timing Reports etc. n-bit Multiplexers Using Verilog can be further implemented for various set of Test Benches. A Test Bench contains different set of input combinations. In future n-bit Multiplexers can be further implemented for increased value of n with multiple Test Bench combinations. n-bit Multiplexers can be designed Using VHDL as well as other HDL languages also and the design can be implemented using Field Programmable Gate Array(FPGA). Keywords: Mux, Verilog, VHDL,HDL, FPGA, RTL, 1. Introduction Multiplexer is a circuit which has multiple inputs and one output. Multiplexer is a combinational circuit. A combinational circuit is a digital circuit whose output is purely a function of its current inputs. Combinational circuit has no memory (past inputs). Multiplexers have been divided into two types Analog Multiplexers and Digital Multiplexers. Analog Multiplexers are multiplexers that multiplex analog signals to get the resultant output signal. Analog multiplexers are manufactured by the components such as relays and transistor switches. Digital Multiplexers are multiplexer that accepts digital signals to yield the output. Digital multiplexers are built from standard logic gates, when the multiplexer is used for digital applications. It is called a digital multiplexer. An analog multiplexer accepts both analog as well as digital inputs, whereas a digital multiplexer accepts only digital inputs. Multiplexer is a Multi input single output circuit. Multiplexers are represented by the notation 2n X 1 or 2n : 1 or 2n to 1 and consists of n select lines. For example an 8X1 Multiplexer has 3 select lines, 8 inputs and 1 output, similarly 16X1 Multiplexer has 4 select lines 16 inputs and 1 output. Multiplexers are called as data selectors. A multiplexer, sometimes called a selector, allows only one of its data inputs Im to pass through to the output O. Allowing only one of multiple input tracks Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3290 https://internationalpubls.com to connect to a single output track. If there are m data inputs, then there are log2(m) select lines S, and an mX1 multiplexer has m data inputs, one data output. For Example an 8X1 Mux has 8- input lines and 1-output line and 3 select lines. The binary value of S determines which data input passes through; • 00...00 means I0 may pass, • 00...01 means I1 may pass, • 00...10 means I2 may pass, and so on. For example, an 8x1 multiplexer has 8 data inputs and thus 3 select lines. If s =111, then I7 will pass through to the output. So if I7 were 1, then the output would be 1; if I7were 0, then the output would be 0. Commonly n-bit multiplexer is used which is a more complex device. Each data input and output, consists of n bits (lines). For Example, a 4-bit 8x1 multiplexer. Thus, if I7were 0110, then the output would be 0110. n is independent of the number of select lines. 2. Objective The objective of the research paper is to develop n-bit Multiplexers: 1-bit 8 to 1 Multiplexer, 8-bit 8X1 Multiplexer and 8-bit 16X1 Multiplexer using Verilog. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3291 https://internationalpubls.com To simulate and synthesize the three Multiplexers using Software Xilinx 14.7 and To obtain the corresponding RTL, Technology Schematics, the design summaries, the Output Waveforms for the given Test bench. 3. Methods 1-bit 8 to 1 Multiplexer:-A Multiplexer 8 to 1 multiplexes eight binary inputs into a 1 bit binary output with 3 select lines. Figure1: Block Diagram of 1-bit 8 to 1 Multiplexer The Block Diagram of 8 to 1 Multiplexer consists of 8 inputs from I7 – Io and output Y with select lines S2 – So. Working of 8 to 1 Multiplexer:- The working of 8 to 1 Multiplexer is as follows, When the select lines input S2S1S0 = 000 and Io is active high/low (Io = 1/0) then the output Y = Io. When the select lines input S2S1S0 = 001 and Io is active high/low (I1 = 1/0) then the output Y = I1. When the select lines input S2S1S0 = 010 and Io is active high/low (I2 = 1/0) then the output Y = I2. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3292 https://internationalpubls.com When the select lines input S2S1S0 = 011 and Io is active high/low (I3 = 1/0) then the output Y = I3. When the select lines input S2S1S0 = 100 and Io is active high/low (I4 = 1/0) then the output Y = I4. When the select lines input S2S1S0 = 101 and Io is active high/low (I5 = 1/0) then the output Y = I5. When the select lines input S2S1S0 = 110 and Io is active high/low (I6 = 1/0) then the output Y = I6. When the select lines input S2S1S0 = 111 and Io is active high/low (I7 = 1/0) then the output Y = I7. Truth table and the logic diagram of 8 to 1 Multiplexer are given as follows. Table1: Truth Table of 8 to 1 Multiplexer Figure2: Logic Diagram of 8 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3293 https://internationalpubls.com Results Figure3: RTL schematic of 1-bit 8 to 1 Multiplexer Figure4: Technology schematic of 1-bit 8 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3294 https://internationalpubls.com Figure5: Output Waveform of 1-bit 8 to 1 Multiplexer Discussion of Results:- From the above output waveform it is clear that, the output Y becomes high based on select lines S2S1So input and the corresponding inputs Io to I7. Table shows the values of select lines and input combinations with the corresponding output. Table2: Truth Table of 1-bit 8 to 1 Multiplexer with 8 input combinations Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3295 https://internationalpubls.com Table3: Timing Summary of 1-bit 8 to 1 Multiplexer Table4: Device utilization summary of 1-bit 8 to 1 Encoder Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3296 https://internationalpubls.com Table5: Primitive and Black Box Usage of 1- bit 8 to 1 Multiplexer 8-bit 8 to 1 Multiplexer:- An 8-bit 8 to 1 Multiplexer multiplexes eight 8-bit binary inputs into an 8 bit binary output with 3 select lines. Figure6: Block Diagram of 8-bit 8 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3297 https://internationalpubls.com The Block Diagram of 8-bit 8 to 1 Multiplexer consists of 8 inputs from I7 – Io and 8-bit output Y with select lines S2 – So. Working of 8-bit 8 to 1 Multiplexer:- The working of 8-bit 8 to 1 Multiplexer is as follows, When the input S2S1S0 = 000 and I7I6I5I4I3I2I1Io = 00000110 then the output Y = 00000110 When the input S2S1S0 = 001 and I7I6I5I4I3I2I1Io = 00101010 then the output Y = 00101010 When the input S2S1S0 = 010 and I7I6I5I4I3I2I1Io = 01000000 then the output Y = 01000000 When the input S2S1S0 = 011 and I7I6I5I4I3I2I1Io = 00010010 then the output Y = 00010010 When the input S2S1S0 = 100 and I7I6I5I4I3I2I1Io = 01111000 then the output Y = 01111000 When the input S2S1S0 = 101 and I7I6I5I4I3I2I1Io = 11011000 then the output Y = 11011000 When the input S2S1S0 = 110 and I7I6I5I4I3I2I1Io = 10010100 then the output Y = 10010100 When the input S2S1S0 = 111 and I7I6I5I4I3I2I1Io = 01110100 then the output Y = 01110100. Table6:-Truth Table of 8-bit 8 to 1 Multiplexer The Truth Table of 8-bit 8 to 1 Multiplexer is given in the following Table. It has 8-bit inputs I0- I7 and three select lines S2 –S0 and 8-bit output Y. Based on select lines input corresponding input flows into output Y. For Example S2S1S0 =100 then Y=01111000 and for S2S1S0 =111 then Y=01110100 and so on. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3298 https://internationalpubls.com Results Figure7: RTL schematic of 8-bit 8 to 1 Multiplexer Figure8: Output Waveform of 8-bit 8 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3299 https://internationalpubls.com Discussion of Results:- The output waveforms are shown in Decimal values. From the above output waveform it is clear that, the output Y becomes one of the inputs Io to I7 based on select lines S2S1So. Table shows the values of select lines and input combinations with the corresponding output. For Example S2S1S0 =100 then Y=120, S2S1S0 =101 then Y= 216 , S2S1S0 =110 then Y= 148 and for S2S1S0 =111 then Y= 116 and so on. Table7: Truth Table of 8-bit 8 to 1 Multiplexer with inputs I0 – I7. Table8: Timing Summary of 8-bit 8 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3300 https://internationalpubls.com Table9: Device utilization summary of 8-bit 8 to 1 Multiplexer Table10: Primitive and Black Box Usage of 8-bit 8 to 1 Multiplexer 8-bit 16 to 1 Multiplexer:- An 8-bit 16 to 1 Multiplexer multiplexes eight 8-bit binary inputs into an 8 bit binary output with 4 select lines. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3301 https://internationalpubls.com Figure9: Block Diagram of 8-bit 16 to 1 Multiplexer The Block Diagram of 8-bit 16 to 1 Multiplexer consists of 8 inputs from I7 – Io and 8-bit output Y with select lines S3 – So. Working of 8-bit 16 to 1 Multiplexer:- The working of 8-bit 16 to 1 Multiplexer is as follows, When the input S3S2S1S0 = 0000 and I7I6I5I4I3I2I1Io = 11100100 then the output Y = 11100100 When the input S3S2S1S0 = 0001 and I7I6I5I4I3I2I1Io = 11001100 then the output Y = 11001100 When the input S3S2S1S0 = 0010 and I7I6I5I4I3I2I1Io = 01110100 then the output Y = 01110100 When the input S3S2S1S0 = 0011 and I7I6I5I4I3I2I1Io = 11100000 then the output Y = 11100000 When the input S3S2S1S0 = 0100 and I7I6I5I4I3I2I1Io = 01101010 then the output Y = 01101010 When the input S3S2S1S0 = 0101 and I7I6I5I4I3I2I1Io = 01101000 then the output Y = 01101000 When the input S3S2S1S0 = 0110 and I7I6I5I4I3I2I1Io = 10111100 then the output Y = 10111100 Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3302 https://internationalpubls.com When the input S3S2S1S0 = 0111 and I7I6I5I4I3I2I1Io = 10000100 then the output Y = 10000100 When the input S3S2S1S0 = 1000 and I7I6I5I4I3I2I1Io = 10110000 then the output Y =10110000 When the input S3S2S1S0 = 1001 and I7I6I5I4I3I2I1Io = 10100100 then the output Y =10100100 When the input S3S2S1S0 = 1010 and I7I6I5I4I3I2I1Io = 11000000 then the output Y = 11000000 When the input S3S2S1S0 = 1011 and I7I6I5I4I3I2I1Io = 01110000 then the output Y = 01110000 When the input S3S2S1S0 = 1100 and I7I6I5I4I3I2I1Io = 10000000 then the output Y = 10000000 When the input S3S2S1S0 = 1101 and I7I6I5I4I3I2I1Io = 01101100 then the output Y = 01101100 When the input S3S2S1S0 = 1110 and I7I6I5I4I3I2I1Io = 10011000 then the output Y = 10011000 When the input S3S2S1S0 = 1111 and I7I6I5I4I3I2I1Io = 10110100 then the output Y = 10110100 Table11:-Truth Table of 8-bit 16 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3303 https://internationalpubls.com Results Figure10: RTL schematic of 8-bit 16 to 1 Multiplexer Figure11: Output Waveform of 8-bit 16 to 1 Multiplexer Discussion of Results:- From the above output waveform it is clear that, the output Y becomes one of the inputs Io to I15 based on select lines S3S2S1So. Table shows the values of select lines and input combinations with the corresponding output. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3304 https://internationalpubls.com Table12: Truth Table of 8-bit 16 to 1 Multiplexer with inputs I0 – I15. Table13: Timing Summary of 8-bit 16 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3305 https://internationalpubls.com Table14: Device utilization summary of 8-bit 16 to 1 Multiplexer Table15: Primitive and Black Box Usage of 8-bit 16 to 1 Multiplexer Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 10s (2025) 3306 https://internationalpubls.com Conclusions Thus n-bit Multiplexers are synthesized and simulated Using Verilog with different Test Benches and the Results are obtained. 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