Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1076 https://internationalpubls.com Optimal Design for High Performance Computing Systems Based on 5-Stage Pipeline 32-bit RISC-V Processor Rajender Kumar1, Sneha Bhattacharya2 1 Assistant Professor, Electronics and Communication Engineering Department, NIT Kurukshetra. India. 2 M. Tech Student, VLSI Design Department, NIT Kurukshetra. India. Article History: Received: 19-03-2025 Revised: 24-07-2025 Accepted: 21-09-2025 Abstract: In an era where computational demands continually escalate, the quest for more efficient and powerful processors persists. Computer engineering and VLSI design industries are facing challenges with the trade-offs between the cost and performance of components in the implementation domain. Reduced Instruction Set Computer (RISC) architecture relies its focus mainly on scaling down the complexity and the number of instructions in the microprocessor. RISC-V is an Open-source Instruction set architecture (ISA) designed to be simple, modular, and customizable. The most important feature of RISC is that it supports load-store architecture. With this feature, an optimized 32-bit microprocessor has been designed with Verilog, simulated and synthesized in Xilinx Vivado. Verilog enables us to describe the behavior and structure of our processor at a register-transfer level. Overall, RISC-V's combination of simplicity, openness, and flexibility positions it as a promising ISA for a wide range of applications, from low-power IoT devices to high- performance computing systems. Keywords: RISC-V, Open-source, Instruction set architecture (ISA), load- store architecture, Xilinx Vivado. 1. Introduction 1.1 Background In the realm of digital design, we embark on a technical exploration aimed at crafting a 5-stage pipeline 32-bit RISC-V processor. At the core of our endeavor lies the 5-stage pipeline architecture, a cornerstone of modern processor design. RISC architecture was introduced with a basic instruction set that had consistent execution times. The added support to load/store architecture makes communication with memories faster and reliable. RISC helps achieve lesser silicon consumption when compared to other design architectures. The pipeline architecture consists of five stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX), Memory access (MEM), and Write-back (WB). Each stage is finely tuned to maximize throughput while minimizing latency. The pipeline incorporates various hazard detection and resolution mechanisms, including forwarding and stall insertion, to ensure correct execution of instructions. 1.2 Problem Statement This paper presents the design and implementation of a 5-stage pipeline 32-bit RISC-V processor, adhering to the specifications of the RISC-V Instruction set architecture (ISA). The processor architecture is optimized for performance, area efficiency, and power consumption. The design is based on a modular approach, facilitating easy integration of additional Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1077 https://internationalpubls.com components and extensions. 2. Objective The primary objective of this paper is to design and analyze a 5-stage pipelined 32-bit RISC- V processor with an emphasis on efficient instruction execution and program counter management. The work focuses on: ● Implementing the instruction execution flow consisting of instruction fetch, decode, execution, ALU operations, and program counter update. ● Demonstrating the role of multiplexers, control logic, and state elements in ensuring correct data flow and instruction sequencing. ● Highlighting how the Program Counter (PC) is updated either sequentially (PC + 4) or through branch offsets (PC + X), with sign-extension and left-shift operations for correct address alignment. ● Ensuring proper utilization of the ALU across instruction classes (R-type, I-type, and memory instructions), except in jump operations. ● Showcasing the benefits of the RISC pipelined architecture in achieving faster and efficient execution by overlapping instruction stages. 3. Instruction Execution in RISC The execution of each instruction in a RISC processor follows a well-defined sequence of steps, ensuring consistent and efficient operation. The detailed stages are outlined below: 3.1 Instruction Fetch ● The Program Counter (PC) is sent to the memory where the code is stored. ● The instruction present at that memory address is fetched. 3.2 Instruction Decode / Register Read ● Based on the instruction fields, required registers are read. ● For a load word (lw) instruction, only one register is needed. ● In most other instructions, two registers are read. 3.3 Execution by Instruction Class ● Once register values are read, execution proceeds according to the instruction class. ● RISC has a simple and uniform instruction classification, allowing proper execution. ● All instructions use the ALU for execution, except the JUMP instruction. 3.4 ALU Operations ● After register values are read, they are sent to the ALU. ● The ALU performs different tasks depending on the instruction type: o I-type instructions (Immediate type): ▪ ALU performs operations such as addition. ▪ The result is stored in the destination register. o R-type instructions (Register type): ▪ ALU performs arithmetic or logical operations using register values. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1078 https://internationalpubls.com o Memory instructions (lw, sw): ▪ ALU calculates the memory address for load/store operations. 3.5 Program Counter Update ● The next instruction address is calculated. ● This comes from one of the two adders (as shown in Fig. 1). ● The updated PC value is sent back to instruction memory for fetching the next instruction. Fig.1 An abstract view of the implementation of the RISC-V subset showing the major functional units and the major connections between them Fig.2 Schematic of RISC-V subset 3.6 Role of Multiplexers, Control Unit, and State Elements in RISC Execution The top multiplexer determines what should be the next address that has to be fetched. Either it could be PC+4 or PC+X where X determines the sign extended address location. The middle multiplexer determines whether the input to the ALU is the second source register or the sign extended value which is used in lw, sw instructions or in branch instructions. The output multiplexer selects whether to output the data back to the instruction memory or the address in Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1079 https://internationalpubls.com the data memory which is to be given to the instruction memory. All the select lines are to be controlled by the control unit. Instruction memory and the Program counter are the state elements. The Instruction Memory can be considered as a combination block. The Program Counter is a 32-bit block which is used to calculate the next instruction to be fetched. Fig.3 The basic implementation of the RISC subset, including the necessary multiplexors and control lines. 3.7 Address Calculation in RISC processor The RISC processor is a 32-bit processor hence all its addresses will be in multiples of 4. For calculating the next instruction bit, the sign extended value can be multiplied by 4 or left shifted by 2 to find the appropriate address by adding with the PC. It is known that the offset has been sign-extended from 16 bits, the shift will give away only sign bits. Control logic is used to find whether the pc should be added by PC+4 or PC+X where X is the sign extended value. Fig.4 Datapath for branch instruction showing ALU-based condition evaluation and branch target calculation using an adder with PC+4 and the shifted, sign-extended offset Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1080 https://internationalpubls.com ALU Control The Arithmetic Logic Unit (ALU) plays a central role in the execution of RISC instructions, performing a variety of arithmetic and logical operations depending on the instruction type: 3.8 Arithmetic and Logical Operations ● For instructions such as addition, subtraction, and logical operations, the ALU directly executes the operation and forwards the result to the data memory or destination register. 3.9 Load and Store Instructions ● In the case of load (lw) and store (sw) instructions, the ALU is responsible for calculating the effective memory address. ● This is achieved by adding the sign-extended immediate value to the base register value obtained from the instruction. 3.10 Branch Instructions ● For branch instructions, the ALU evaluates the specified condition. ● If the condition is satisfied, the ALU computes the target address and updates the Program Counter (PC) to jump to the branch location. 3.11 ALU Control Mechanism ● The ALU is governed by a 4-bit ALU control signal, which determines the specific operation to be performed. ● Among these control bits, the last two bits are designated as the ALUOp, which provide higher-level instruction classification (e.g., R-type, branch, memory access). ● For R-type instructions, the exact ALU operation is further refined using the 6-bit function (funct) code from the instruction field. Fig.5 ALU control signal generation based on ALUOp control bits and function codes for R- type instructions Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1081 https://internationalpubls.com 4. Main Control Unit The control unit is responsible for generating all control signals required for instruction execution. These signals are primarily determined by the opcode field of the instruction (bits 31–26), with the exception of the PCSrc control line, which is influenced by the branch control logic. The PCSrc line is specifically used to select the branch predictor output. 5.1 Inputs to the Control Unit ● The opcode field (6 bits) is provided as input to the control unit. ● Based on this input, the control unit generates the necessary control signals to regulate the datapath. Fig.6 Schematic of the control unit. 5.2 Control Signals A total of eight control signals are produced, which serve as inputs to different components of the processor. These include: ● RegWrite: Determines whether a value is written into the register file. ● ALUOp: Directs the ALU control block to perform the required arithmetic or logical operation. ● MemRead / MemWrite: Control signals for data memory, selecting whether to read from or write into memory. ● MemToReg: Select signal for the multiplexer that decides whether the data to be written back to the register comes from the ALU or from memory. ● ALUSrc: Select signal that determines whether the ALU’s second input is taken from a register or a sign-extended immediate value. ● PCSrc: Selects whether the next PC value is PC + 4 (sequential execution) or PC + X (branch Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1082 https://internationalpubls.com execution). Fig.7 The simple Datapath with the control unit. 5. Pipelined Datapath And Control Pipelining is a fundamental design technique in RISC architectures, enabling parallel execution of instructions by dividing the instruction cycle into distinct stages. In a 5-stage RISC pipeline, multiple instructions are executed simultaneously, with each stage processing a different instruction. This significantly reduces the overall execution time for a sequence of instructions. The five stages of the RISC pipeline are as follows: 5.1 Instruction Fetch (IF) ● The instruction fetch stage retrieves the instruction from instruction memory using the address stored in the Program Counter (PC). ● The PC is then updated (typically PC + 4) to point to the next instruction. 5.2 Instruction Decode and Register File Read (ID) ● The fetched instruction is decoded to determine its type and operands. ● The required registers are read from the register file. ● This stage also prepares data for possible write-back to registers. Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1083 https://internationalpubls.com Fig.8 The pipelined Datapath with the control signals identified 5.3 Execution or Address Calculation (EX) ● The ALU performs arithmetic or logical operations as defined by the instruction opcode. ● For memory-related instructions, the ALU calculates the effective address by adding the sign-extended immediate value to the base register. 5.4 Memory Access (MEM) ● If the instruction requires memory access, the data memory is addressed using the result from the ALU. ● For load instructions (lw), data is read from memory. ● For store instructions (sw), data is written into memory. 5.5 Write-Back (WB) ● The final stage updates the register file with the result of execution. ● For arithmetic/logical instructions, the ALU result is written back. ● For load instructions, the value fetched from memory is written back to the register. Fig.9 Schematic of Register unit of pipelined datapath Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1084 https://internationalpubls.com 6. Hazard Detection And Stalling Pipeline hazard are some situations in which the instructions are such that the pipeline cannot happen in the normal way and we need to stop for some clock cycles in order to properly execute the operations. There are mainly 3 different types of hazards: 6.1 Structural Hazard This type of hazard occurs if the data memory and instruction memory are not separate. Hence in the fourth stage when there will writing to the data memory, some instruction might read from the instruction memory. Since reading and writing from the same memory at the same time is practically not possible in the same control cycle, this gives rise to Structural Hazard. 6.2 Data Hazard Let us consider an example: add t0, t1, t2 add t4, t0, t3 Now from the above example we can see that after the execution of first instruction we would get the value of t0 which can be used in the execution of the second instruction. Hence either we need to stall the second instruction till the execution unit of the first or do forwarding in which the as soon as the execution happens the data is sent to the instruction decode stage thereby saving a clock cycle. 6.3 Control Hazard Consider the following example: beq t0, t1, L1 Sub t0, t1, t2 L1: add t3, t4, t5 From the above example, we can see that after the first instruction execution, we would get that which instruction we can execute or not. So either we need to stall the next instruction fetch after the execution unit or we use branch predictors. In branch predictors, we have schemes from which we can select if branch is taken or not in the beginning of the instruction fetch and proceed accordingly. If after the execution unit result, the prediction is alright, then we can proceed accordingly. If the prediction is false we need to flush the entire instruction and again proceed with the correct instruction. Fig.10 Hazard Detection Unit Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1085 https://internationalpubls.com In our processor design, hazard detection primarily addresses two categories of hazards: data hazards and control hazards. Data hazards occur when an instruction attempts to use a value that has not yet been updated, leading to incorrect computations. To detect such conditions, the design checks whether the destination register of the EX/MEM stage matches either of the source registers of the ID/EX stage. This is expressed as the condition: (ID_EX_Rt == IF_ID_Instr[25:21]) || (ID_EX_Rt == IF_ID_Instr[20:15]) When this condition is met, control signals are generated accordingly. The holdPC signal ensures that the Program Counter (PC) retains its current value, thereby preventing the fetch of the next instruction. Simultaneously, the IF/ID pipeline register holds its previous value, and the control signals are zeroed out to effectively stall subsequent stages. Control hazards arise in branch instructions, since the outcome of a branch can only be determined in the execution stage. By this time, the following instruction has already begun execution, leading to potential inconsistencies. To handle this, the design either stalls the pipeline until branch resolution or flushes instructions that were incorrectly fetched. Fig. 11 Forwarding Element Fig. 12 Schematic of Forwarding Unit Forwarding is employed to further mitigate data hazards. If the control signals MemRegWrite and MemWriteReg from the EX/MEM stage are active, and the destination register (MemWriteReg) matches the source register (Rs) of the ID/EX stage, a forwarding signal is generated. This enables the ALU output from an earlier stage to be directly forwarded to the dependent instruction, ensuring correctness without waiting for the write-back stage. Similar Communications on Applied Nonlinear Analysis ISSN: 1074-133X Vol 32 No. 3 (2025) 1086 https://internationalpubls.com checks are performed for the Rt register as well. Additionally, if the register being written to in the final stage coincides with the register currently being accessed, the forwarded value is taken from the last multiplexer output instead of the register file, since the register file still contains an outdated value. 7. Simulation Results The simulation waveform shown in Fig. 13 validates the functionality of the designed 5-stage pipelined 32-bit RISC-V processor. The clock (clk) and reset (reset) signals operate as expected, ensuring proper synchronization and initialization of the pipeline. The Program Counter (nextPC, readPC, PCPlus4) increments correctly in steps of 4, confirming sequential instruction fetch. Fig. 13 Simulated timing diagram of top-level module Overall, the timing diagram confirms that: ● The Program Counter is updated correctly in each cycle. ● Instruction fetch, decode, execute, memory, and write-back stages function as intended. ● Register values are updated with accurate results after execution. ● Hazard detection and forwarding mechanisms successfully prevent data inconsistencies. Thus, the waveform verifies the functional correctness and pipeline efficiency of the implemented RISC-V processor. 8. Conclusion and Future Scope In this work, a 5-stage pipelined 32-bit RISC-V processor has been designed and implemented in Verilog on the Xilinx Vivado platform, incorporating a hazard detection unit to efficiently resolve data and control hazards, thereby minimizing pipeline stalls and enhancing execution throughput. The processor supports fundamental instruction types such as R-type, I-type, load/store, and branch instructions while maintaining strict compliance with the RISC-V ISA, ensuring seamless software compatibility. Comprehensive simulation and validation confirmed the functional correctness of the design, along with notable improvements in performance, low area utilization, and reduced power consumption achieved through architectural optimization. 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