Engineering, Technology & Applied Science Research Vol. 7, No. 6, 2017, 2251-2255 2251 www.etasr.com Asl et al.: A Gain Programmable Analog Divider Circuit Based on a Data Converter A Gain Programmable Analog Divider Circuit Based on a Data Converter Shahin Navabi Asl Department of Electrical Engineering Damghan Branch Islamic Azad University Damghan, Iran setare64.navabiasl@gmail.com Mahdi Tarkhan Department of Electrical Engineering Zahedan Branch Islamic Azad University Zahedan, Iran m.tarkhan@gmail.com Mojtaba Shokohi Nia Department of Electrical Engineering Damghan Branch Islamic Azad University Damghan, Iran mshokohinia@damghaniau.ac.ir Abstract—Analog dividers are widely used in analog systems. Analog realization of such circuits suffer from limited dynamic range and non-linearity issues, therefore, extra circuitry should be required to compensate these types of shortcomings. In this paper a gain controllable, analog divider is proposed based on data converters. Our circuit can be implemented both in current and voltage mode by selecting proper architectures. The resolution, power consumption and operation speed can be controlled by proper selecting of components. Another advantage of our circuit is its gain programmability. Moreover, the gain can be adjusted independently based on the relationship between input signals. Our proposed method offers two different gain control abilities, one for situation that the numerator signal is bigger than the denominator, and another gain is applied when the denominator is larger than the numerator. As a result, no extra amplifier is required for signal amplification. Moreover, the input and output signal nature can be chosen arbitrarily in this circuit, i.e. input signal may be a voltage signal while the output signal is current. Simulation results from SPICE confirm the proper operation of the circuit. Keywords-analog divider; data converter based divider; gain adjustable analog divider; wide dynamic range analog divider; mixed signal divider I. INTRODUCTION Dividers are a basic building block in analog signal processing systems. Such a system usually requires high precision dividers to realize modulators, squarers, automatic level controllers, etc. Several techniques are proposed in the literature to design dividers in continuous time monolithic circuits from different technologies. CMOS dividers are reported both in the strong and weak inversion. Strong inversion approaches are very complex in signal interfacing point of view [1-7]. On the other hand, weak inversion circuits are slow [8-13]. Some researchers design dividers working in voltage mode, while current mode circuits can achieve lower power consumption, higher dynamic range and linearity. An alternative approach is using switched capacitor technique [14]. Authors in [15] proposed a novel method of realization of voltage mode analog multiplier/divider based on the modified cyclic data converter. A current mode multiplier/divider in current mode utilizing data converter techniques is presented in [7]. In this paper, a novel divider circuit is proposed based on data converters. There is a trade-off between speed, power consumption and resolution that can be managed by properly selecting the components used. Furthermore, our proposed circuit can produce the output signal with controllable gain. Two conditions might occur in dividers, the numerator signal is larger than the denominator‘s and vice versa. The gain of our proposed circuit can be adjusted independently in both conditions via a control signal and hence, offers the maximum level of gain adjustability. II. PROPOSED CIRCUIT Suppose x and y are analog signals (current or voltage) and our goal is to produce a signal that is proportional to the division of x and y as follows: y x kz    where x in the numerator, y is the denominator, k is the gain of division and z is the final output. The straightforward solution to realize a divider is to use the analog dividers. However, as it was mentioned earlier, analog dividers have some limitations. Another solution is the use of digital signal processor, nevertheless, this method requires two ADCs to convert input signals to digital and a DAC to produce the analog signal from the division result. Our proposed circuit needs only an ADC and a DAC with similar resolution as depicted in Figure 1. The ADC sampled and converts the input signal (xnum) based on its reference signal level (xden) and its resolution (N bits) as follows:  2 den num N x x B   where B is an N-bit digital code. Applying the digital code to a DAC with similar resolution results to producing an analog signal as represented in (3). Engineering, Technology & Applied Science Research Vol. 7, No. 6, 2017, 2251-2255 2252 www.etasr.com Asl et al.: A Gain Programmable Analog Divider Circuit Based on a Data Converter 2 ref out N x x B   Solving (2) and (3) we come to (4): num out ref den x x x x    with the quantization error of 1/ 2Ndenx  . Two situations might occur: numerator is bigger than the denominator and vice versa. They can be considered separately. A. Denominator is Bigger Than the Numerator (y>x) In this situation, the output signal resulting from (1) is less than k. Figure 2 shows the proposed circuit configuration to produce the output signal in this mode. Denominator signal (y) is connected to the reference signal pin of ADC (xden) and Numerator (x) is connected to the input of the ADC (xnum). ADC voltage source (k1) is connected to the reference signal of the DAC, and the final output is appeared on the output of the DAC based on (5). 1 x z k y     Since in this mode, xy) In this situation, the division result is greater than k. The connectivity diagram of the circuit in this mode is illustrated in Figure 3. In this situation, x is used as reference voltage of ADC (xden) and y is connected to the input of ADC (xnum). Equation (6) shows the final output produced by DAC.  out ref y x x x    Since x>y so the output swings from zero to xref like the first mode. The output signal generated in this mode is the inverse of the desired signal. Finding xref from above equation we have:  ref out x x x y     DAC produces an analog signal based on its resolution, reference signal and the applied digital code. The digital code is already produced by ADC and is constant between cycles. Suppose we compare the xout signal with a constant signal (e.g. k2). Rising xref gradually from zero, increases the output signal (xout) as well. At the time that the output signal reaches k2, the xref signal has a value proportional to the division result as proved in (8).  2ref x x k y     So the xref is the scaled version of desired output (z). ADCs have internal sample and hold that capture the input signal at the specific time produced by a clock generator. Then the conversion process is performed on the sampled signal. Our proposed circuit is suitable to be used in the sampled analog system in which the output signal is valid in specific time and between time slices, the signal processing is done in internal circuits. Therefore, between time steps, the digital code produced by ADC would not change. A ramp generator is used to produce the reference signal for DAC. It's simply a sawtooth signal generator with reset capability. Since the digital code is not changing, increasing the xref signal results in increasing the output of the DAC as well. The output signal produced by DAC is compared by a constant value (i.e. k2) by a comparator. When the output signal is low, the comparator output is at the low saturation level, too, and the switch is opened. Increasing the xref, increases the xout and this process is performed until the positive and negative voltages of comparator become equal. At this time, the comparator output signal flips to high saturation level. Consequently, the switch turns on and xref connected to the output pin (z). Meanwhile, the ramp generator is being reset in order to start the new cycle, resulting in decreasing xout and turning off the switch. Figure 4 depicts the internal structure of the ramp generator. The sawtooth signal is generated by a PMOS current source (MP1) and an integrating capacitor (C). NMOS switch is connected in parallel to the capacitor in order to discharge it during reset phase. Since xclk and enable signals are not allowed to be activated simultaneously, direct current path from Vdd to gnd cannot be created, which means no extra static power is dissipated. It is worth mentioning that ramp generator is solely used in second mode where the numerator is bigger than the denominator. Using enable signal makes it possible to deactivate the circuit in the first mode. C. Complete Circuit Combining the abovementioned circuits, the final structure of the proposed circuit can be achieved as shown in Figure 5. Engineering, Technology & Applied Science Research Vol. 7, No. 6, 2017, 2251-2255 2253 www.etasr.com Asl et al.: A Gain Programmable Analog Divider Circuit Based on a Data Converter This circuit has two signal paths that activate based on the modes describe before. This is done by comparing the numerator and denominator signals. Analog multiplexers are used to form the signal path. In Figure 5, the input signals are compared by the comparator (Comp2) which generates the sel signal. Suppose x is greater than y then sel would be at low saturation level results in selecting the zero line of the multiplexers. Therefore, y signal is applied to the input and x is applied to the reference of ADC. This is the second mode which utilizes the ramp generator. Hence the ramp generator is enabled by the sel signal (turning on MP2), and the sawtooth signal (xramp) is applied to the reference of the DAC (xref). In this configuration, the xref signal is applied to the output pin through Mux4 (z=xref). As it is mentioned earlier, this signal is equal to the division result scaled by k2. If xy). BufferCMN1 MP1 Enable Xclk Out Bias MP2 Fig. 4. Internal structure of the ramp generator. EnableOut xclk Ref Ref in inout out DAC n Comp2 K2 M ux 1 M ux 2 Ramp Generator Comp1 ADC K1 Z sel sel sel sel sel sel xref y x y x x y xramp xout xoutxclk M ux 4 M ux 3 Y X 0 00 0 1 1 1 1 Fig. 5. The complete structure of the proposed circuit. TABLE I. DATA CONVERTER SELECTION GUIDE Input signal Output signal ADC type DAC type voltage voltage Voltage mode Voltage mode voltage current Voltage mode current mode current voltage current mode Voltage mode current current current mode current mode III. SIMULATION RESULTS The proposed circuit is simulated in HSpice. The generic model of ADC and DAC with 8-bit resolution is used in the simulation environment. The transient simulation is done in three different conditions. A. State 1 (xy) In this state, the numerator is fixed at 120mV using a DC source, while a 1kHz sine wave with 20mV AC amplitude and 0.1V of DC offset is applied to the denominator input pin as depicted in Figure 8a. Figure 8b shows the ideal as well as the actual output signal when the sampling frequency is 10kHz. The output signal generated by DAC (xout) and the comparator output (xclk) are illustrated in Figure 8c. When the xref is rising from zero, xout increases as well. This process continues until xout is becoming equal to k2, where the xout has a value equal to the division result. Simultaneously, the comparator output flips to high saturation level disabling the ramp generator. Halving the k2 signal to 0.5V, halving the final output as well as illustrated in Figure 8d. Engineering, Technology & Applied Science Research Vol. 7, No. 6, 2017, 2251-2255 2254 www.etasr.com Asl et al.: A Gain Programmable Analog Divider Circuit Based on a Data Converter x y V (V ) .2 .4 .6 .8 1.0 1.2 1.4 time (us) 0.0 100.0 200.0 300.0 400.0 Fig. 6. Numerator (green) and denominator (red) signals applied to the circuit in 1st state (x