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www.etasr.com Al-Ateeq & Alateeq: Soft-Charging Effects on a High Gain DC-to-DC Step-up Converter with PSC Voltage 

 

Soft-Charging Effects on a High Gain DC-to-DC 

Step-up Converter with PSC Voltage Multipliers 
 

Ayoob S. Al-Ateeq 

Electrical Engineering Department 
Univerity of Hail 

Ha’il, Saudi Arabia 

Abdulaziz J. Alateeq 

Electrical Engineering Department 
Univerity of Hail 

Ha’il, Saudi Arabia 

 
 

 

Abstract−This paper proposes a split-phase control diagram for a 

new design of a DC-to-DC boost converter which is called PSC-

boost and studies its performance. The PSC-boost has two sides, 

the primary is a PSC converter and the secondary is a DC-to-DC 

boost converter. The effect of applying the split-phase control 

diagram helps reduce the output impedance successfully and 
increases efficiency by 3%. The simulated and analytical results 

have been proven to validate the effect of the split-phase diagram. 

The simulated design contains five switches, five capacitors, seven 

diodes, and three inductors to step up 10V into 160V at 200KHz 

and 100KHz switching frequencies. The LTspice simulator was 
used to design and test the proposed model. 

Keywords-PSC-boost converter; split-phase diagram; SC 

converters; LTspice  

I. INTRODUCTION  

Renewable energy has been proven to be an essential 
sustenance of conventional energy resources. Sustainability and 
eco-friendliness are two motivations that motivate hundreds of 
renewable energy research projects, but the low produced 
power limits its usage, for instance, PV cells produce a voltage 
that ranges between 12 to 48V. To overcome this limit and 
expand renewable energy applications, boosting the DC 
produced voltage to a higher voltage level by using DC-to-DC 
boost converters is recommended. Furthermore, DC-to-DC 
converters help finding the appropriate integration between 
renewable energy sources and grid utilities. There are two types 
of DC-to-DC boost converters: isolated or non-isolated 
converters. Their main difference is that the isolated design has 
a power transformer that divides the converter into primary and 
secondary sides. Having a power transformer increases the 
voltage gain, however it can produce electromagnetic 
interference. Lower power density is another side effect of 
using a power transformer. Thus, a non-isolated conventional 
boost converter is preferable over the isolated DC-to-DC 
converter due to the absence of the power transformer. Duty 
cycle dependency and voltage inductor second balance are two 
operational aspects of the non-isolated boost converter. The 
proportional relation between the duty cycle and high voltage 
gain makes the increase in the duty cycle the only way to 
provide a higher voltage gain. However, the increase of duty 
cycle is limited by switches’ voltage stress, which could harm 
the converter’s efficiency. There are several alternative ways to 

increase the voltage gain at a lower duty cycle, such as adding 
voltage multipliers to the DC-to-DC boost converter [1, 2]. 
Besides that, using a resonant approach for DC-to-DC 
converters, shows great improvement of the converters 
efficiency [3, 4]. The new DC-to-DC converter is known as a 
Multilevel Boost Converter (MBC). Adding more output 
multipliers and keeping the main converter part (primary side) 
is the main aspect of the MBC converter [5-13]. The MBC 
increases the regulated output voltage by adding voltage cells, 
which are basically switched capacitors cells, but have 
drawbacks, such as the failure to produce the actual output 
voltage at higher duty cycles [14]. The proposed model in [14] 
uses a switched capacitor converter (PSC) as a primary stage 
on a conventional boost converter. The switched capacitors 
cells work similarly with the MBC converter, however, they 
are connected to the primary side of the conventional boost 
converter. The PSC-boost converter has shown superiority in 
the efficiency and actual rated voltage achievement in 
comparison with the MBC converter. In [15], the proposed 
control diagram helps achieving the complete soft-charging 
operation. The proposed split-phase diagram helps in 
increasing the efficiency by reducing the PSC converter’s 
output impedance. 

This paper complements our work in [14] by using a split-
phase control diagram [15] to operate the 8 switches of the 
PSC-boost. The implemented control diagram increases 
effectively the PSC-boost efficiency in reducing the output 
impedance. Analytical and simulated results are presented. 

II. THE PSC SWITCHED-CAPACITOR CONVERTER 

A. Topology and Operation 

Figure 1 shows the topology of the 1-to-4 PSC converter 
and its control signals. The control diagram in Figure 2(a) 
shows how four modes of operation are possible. In each mode, 
the capacitors are connected to each other differently for 
voltage regulation purposes. In Mode-1, the flying capacitor Cf1 
is charging and the flying capacitor Cf2 is discharging. In 
Mode-2, both flying capacitors Cf1 and Cf2 are discharging and 
in Mode-4 they are both charging. In Mode-3 Cf1 is discharging 
and Cf2 is charging. To find the gain voltage of the proposed 
converter, each mode has a total charge that can be derived 
from the following equations [15-18]: 

Corresponding author: Ayoob S. Al-Ateeq (a.alateeq@uoh.edu.sa)



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��� � ����	 
�����
��
���	 
 ������    (1) 
where � is the number of modes (1, 2, 3, 4). From Mode-1 
(Figure 2) we have:  

��
� � ���    (2) 
��� � ��
�     (3) 

��
� � �� � ��� � ��
�    (4) 
B.y substituting (2), (3) and (4) in (1) we get the total 

charge of Mode-1 (5): 

��	 � �������	 � �	� 
 
������ 
��� � �	 � ��	� 
 ����	 
 ��	�     (5) 

To find the total charge of the rest of the modes, the same 
steps can be repeated: 

��� � ������	 � �	� 
�����	 
 ��� � ��� 
������    (6) 
��� � �������	 � �	� 
 

�����	 
 ��	 
 ��� � ��� 
 ������     (7) 
��� � ������	 � �	� 
 

������	 
 ��� 
��� 
 �����	     (8) 
 

 
Fig. 1.  The 2-level of the proposed PSC-boost converter. 

In the steady state operation, the total charge of any pair of 
modes is assumed to be equal. In this work, we assumed that:  

��	 � ���    (9) 
��� � ���    (10) 

By simplifying (9) and (10) we get: 

2�����	 
 �����	 � ������	 � 0    (11) 
2�����	 � �����	 � 0    (12) 

By combining (11) and (12), the 1-to-4 PSC converter’s 
voltage gain can be calculated (13): 

	���� � 4���    (13) 
The general form of the proposed converter is: 

	���� � 2����    (14) 
where � is the number of the stage.  
B. Slow-Switching Limit Impedance (Rssl)  

The SC converters suffer from losses related to the 
switches’ switching and the capacitors’ charging or discharging 
process. This capacitors’ loss can be characterized as an output 
impedance that is called a slow switching limit impedance  !!". 
The charge flow analysis of the four modes has been applied to 

find the charge multiplier of the four capacitors #$�   
%$� � #$� 	%���    (15) 

%$ � &%��%��%�
�%�
�'(    (16) 
In [13, 14] a useful technique was used to find the charge 

flow’s vector of all the operation modes. For the ith mode, 
KCL can be derived by: 

)�%� � 0    (17) 
where )� represent the reduced incidence matrices of the four 
modes of 1-to-4 PSC converter: 

1 1 0 1 0 0 1 1 0 1 0 0

0 1 1 1 1 0 0 1 1 0 1 0
       1 2,

0 0 1 0 1 1 0 0 1 0 0 1

1 0 0 0 0 1 1 0 0 1 1 1

1 1 0 1 0 0 1 1 0 1 0 0

0 1 1 1 1 0 0 1 1 0 1 0
   3, 4,

0 0 1 0 0 1 0 0 1 0 1 1

1 0 0 0 1 1 1 0 0 1 0 1

B B a

B Ba a

− − − − −   
   − − −   = =
   − − − −
   
      
− − −   
   − − − − − −  = =
  − −
  

−     






    (18) 

To find the charge flow’s vectors, (17) can be solved for %�: 

%*"�+	 �

,
-
-
-
-
.�31
�1
�2
2
3 1
2
2
2
2
3
	    %*"�+� �

,
-
-
-
-
.�31
�3
2
�2
3 1
2
2
2
2
3
    %*"�+� �

,
-
-
-
-
.�2�1
3
1
�1
3 1
2
2
2
2
3
	    %*"�+� �

,
-
-
-
-
.�2�3
2
1
1
3 1
2
2
2
2
3
    (19) 

The total output charge with respect to the output charge 
can be found in (20): 

%��� � %���	 
%���� 
 %���� 
 %����     (20) 
The total output charge with respect to the input charge is: 

%��� � %�� 
 %�� 
 �456�  +
�456
�  = 5%��    (21) 

By using (21), (19) can be rewritten with respect to the 
output charge (22): 

%$	 �

,
-
-
-
-
.
489:
;

<489:
;

<�489:
;

�489:
; 1

2
2
2
2
3
	     %$� �

,
-
-
-
-
.
489:
;

<�489:
;

�489:
;

<489:
; 1

2
2
2
2
3
    %$� �

,
-
-
-
-
.
<489:
;

�489:
;

489:
;

<489:
; 1
2
2
2
2
3
	    %$� �

,
-
-
-
-
.
<�489:

;
�489:
;

489:
;

489:
; 1

2
2
2
2
3
    (22) 

By applying (15), the charge multipliers are: 



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#$	 �

,
-
-
-
-
.
	
;
<	
;
<�
;
�
; 1
2
2
2
2
3

	    #$� �

,
-
-
-
-
.
	
;
<�
;
�
;
<	
; 1
2
2
2
2
3

    #$� �

,
-
-
-
-
.
<	
;
�
;
	
;
<	
; 1
2
2
2
2
3

    	#$� �

,
-
-
-
-
.
<�
;
�
;
	
;
	
; 1
2
2
2
2
3

    (23) 

Then by using Tellegen’s theorem,  !!" can be found for 
the proposed design: 

=89:
489:


 ∑ �?@,5�
�

�5
��BCDE	��	�
�F	 � 0    (24) 

where  
=89:
489:

�  !!". 

 !!" � ∑ �?@,5�
�

�5
��BCDE	��	�
�F	     (25) 

 
Fig. 2.  1-to-8 PSC topology (three-stage). 

 
Fig. 3.  The charge flow direction for each operation mode. 

C. Fast-Switching Limit Impedance 

Another important parameter in the SC converters’ analysis 
is finding the fast switching limit ( *!"). In the SC converter 
two parameters are responsible for increasing efficiency, which 
are high switching frequency and large capacitor size. The  *!" 
depends on the switches’  G!_�� as: 

 *!" � ∑ 	�#E,�����BCDE	��	I�F	     (26) 
where �#E,�� is the charge multiplier of eight switches in the 1-
to-4 PSC converter. 

III. A COMPARISON BETWEEN THE PROPOSED PSC 
CONVERTER WITH THREE SC CONVERTER TOPOLOGIES 

The comparison between the proposed PSC and three 
known SC converter topologies (1-to-4 series to parallel, 1-to-4 
ladder, and 1-to-4 Dickson) considers the fundamental 
efficiency and the output impedance. The PSC converter is 
found to be superior over the three other topologies in high 
efficiency achievement whereas the 1-to-4 ladder has the 
lowest efficiency (Figure 4). In addition, the PSC converter 
successfully achieves the SSL limit at a lower switching 
frequency faster than the other topologies (Figure 5). In other 
words, the PSC converter requires less switching frequency to 
achieve lower output impedance. The second lowest output 
impedance among the compared topologies is accomplished by 
the series to parallel topology, which means that an additional 
comparison must be calculated between the PSC converter and 
1-to-4 series to parallel considering the number of switches and 
the maximum voltage stress across the switches [19-24].  

 

 
Fig. 4.  Efficiency vs rated power. 

IV. THE PROPOSED MODEL 

The PSC switched-capacitor converter can be used as a 
voltage multiplier and as a primary stage of a non-isolated 
boost converter. The multiplier cells can be increased with 
regard to the desired output voltage without distorting the 
conventional boost converter side. Capacitors’ charging and 
discharging processes are successfully demonstrated by fully 
controllable semiconductor devices, which are switches. The 8 
switches are controlled by the proposed split-phase diagram 
that allows dead time for each switch. In addition to applying a 
split-phase control diagram, the proposed switched inductor 
cell in [25] is used as an input inductor in the boost converter 
side (second-stage). The proposed control diagram is based on 
the increase of the periods of the transitions modes which are 
between any two existing modes. This allows a dead time for 
all eight switches (Figure 3). Applying the split phase control 
diagram helps to reduce the output impedance, thus exhibiting 
the converter’s efficiency. Adding more modes would reduce 
the charge multipliers of each capacitor and thus reduce the 



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output impedance. To reduce the output impedance by using 
the convectional control diagram requires a higher switching 
frequency. This requirement can be recovered by applying the 
split-phase control diagram where the output impedance can be 
maintained low at a lower switching frequency. Table I exhibits 
the comparison between the PSC output impedance for 
traditional and split-phase control diagrams.  

 

 
Fig. 5.  Output impedance vs switching frequency. 

TABLE I.  COMPARISON BETWEEN THE PSC OUTPUT IMPEDANCE 
FOR TRADITIONAL AND SPLIT-PHACE CONTRO 

Charging operation JKKL �MN,O�P 

Conventional control diagram 
1
6 R

�#$,���
��	STU

��BCDE	��	�

�F	
 

5
2 

Split-phase control diagram 
3
20 R

�#$,���
��	STU

��BCDE	��	�

�F	
 

5
18 

 

V. ANALYSIS OF THE PROPOSED MODEL 

The proposed converter has two stages, PSC converter and 
conventional boost converter (Figure 7). The boost stage has an 
input which is basically the PSC converter output voltage. 
When replacing the input inductor of the boost converter by the 
switched-inductor model which has three inductors W	, W� and 
W�, these three inductors are assumed to be ideal and equal. 
During Mode-1 to Mode-4, each of the three inductors has a 
voltage drop equal to ��� (27) due to their parallel connection: 

	��� � �X	 � �X� � �X�    (27) 
Y$ � <=89:Z[     (28) 

where ����  and  X  are the output voltage and the load 
respectively. When S-boost is off, a series connection of W	, W� 
and W� is exhibiting through Mode-5 to Mode-8: 

��� � �X	 
 �X� 
 �X� 
 ����    (29) 
since W	 , W�  and W�  are the same, they will have the same 
voltage drop.  

	��� � �X	 
�X� 
 �X� 
 ����     (30) 
3�X � �X	 
 �X� 
 �X�    (31) 

We can rewrite (30) into (31) to get (32): 

��� � 3�X 
 ����    (32) 
�X � =56<=89:�     (33) 

By assuming the inductor voltage’s second balance to (27) 
and (33), the voltage gain of the proposed model can be 
obtained: 

	\��� � ��1 � \��=56<=89:� �    (34) 
The converter gain of the second stage can be found by:  

=89:
=56

� �]^		<]     (35) 
By substituting ��� in (35) by the output voltage of PSC we 

get: 

=89:
=89:__`a

� �]^		<]     (36) 
����_bI� � 2c���    (37) 

where N is the number of the converter stages.  

 

(a) 

 

(b)  

 

Fig. 6.  (a) A proposed timing diagram for the split-phase operation for the 

1-to-4 PSC converter, (b) The 8 operation modes of the 1-to-4 PSC converter 

after applying the split-phase. 



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Fig. 7.  The proposed converter and its two stages, PSC converter and 

conventional boost converter. 

By rewriting (36), the voltage gain of the PSC-boost 
converter can be represented as: 

=89:
=56

� �d��]^	�	<]     (38) 
 

VI. RESULTS AND DISCUSSION 

LTspice simulator was used to study the PSC-boost 
converter and its performance in split-phase control. Based on 
the simulation parameters in Table II, the two-level PSC-boost 
converter successfully converts 10V to 160V as presented in 
Figure 8.  

TABLE II.  SIM ULATION PARAMETERS O F THE PSC-BOOST  

Parameter Value 

Input voltage (V) 12V 

Switching Frequency Boost (kHz) 100 

Switching Frequency S1 to S8 (kHz) 200 

Diode type MBRS240LT3 

Switches type IRFI540NPbF 

C1 to C7 94µF 
Cf1, Cf2 and Co 188µF 

Duty cycle of Sboost 50% 

 

 
Fig. 8.  The output voltage of the proposed PSC-boost converter. 

Furthermore, the single inductor in the boost side was 
replaced by a switched inductor model to increase the proposed 
converter’s gain and its rated output power. The switched-
inductor cell operates in two operation modes regarding to the 

Sboost states. The three inductors have a parallel connection 
when Sboost is on and a series connection when Sboost is off. 
Having parallel and series connections allows inductors to 
charge and discharge instantaneously. The dependency 
between Sboost states and inductors’ connections can be proven 
by the waveform similarity between the switched inductor 
input current and the Sboost gate driver, as indicated in Figure 9.  

 

 

Fig. 9.  Yin with the duty cycle, shows W1, W 2 and W3 parallel and series 
connections. 

 
Fig. 10.  The output impedance at two different control diagrams. 

 
Fig. 11.  The efficiency of PSC multiplier cells at two different control 

diagrams. 

Since the PSC-boost converter consists of two stages (SC 
cells and a conventional DC-to-DC boost converter), in this 



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article the primary stage of PSC cells was designed to operate 
in the complete soft-charging operation [13, 15]. The complete 
soft-charging operation effectively reduces the switching 
frequency requirement that is essential to decrease the SC 
converter’s output impedance as presented in Table I. 
However, in order to achieve the complete soft-charging 
operation, a split-phase control diagram is needed. The split-
phase diagram presents a transition mode between any two 
existing modes in the conventional operation. For instance, a 
transition mode, called Mode-1b, will appear between Mode-1 
and Mode-2. The difference between Mode-1 and Mode-1b is 
that Mode-1b has three capacitors instead of four. The isolation 
of the fourth capacitor reduces the total charge multipliers, and 
as a result, lower output impedance will be achieved. 

The work in [14] has been completed in this paper. The 
PSC converter is controlled by the split-phase control diagram 
instead of its conventional operation. Figure 10 shows a 
comparison of the PSC converter’s output impedance before 
and after using the split-phase control diagram. It can be clearly 
seen that using a split-phase control diagram helps to reduce 
the output impedance and as a result a lower switching 
frequency is required to reduce the capacitors’ losses. In 
addition to the output impedance reduction and low switching 
frequency requirement, the spilt-phase operations increase the 
converter’s efficiency. The reduction of the output impedance 
which represents the SC converter loss is behind the high 
efficiency achievement.  

VII. CONCLUSION 

The LTspice simulator has been used to design the 
proposed model and successfully produces a 160V from 10V 
input. The effect of using a split-phase control diagram to 
improve the efficiency of the PSC-boost converter was proven 
in this article. The spilt-phase control diagram reduces the 
switching loss and the output impedance. The split-phase 
control diagram was compared with the conventional control 
diagram in [9] and the efficiency effectively increased from 
92% to 95%. This superior efficiency achievement is caused by 
the lower output impedance and dead time periods. In addition, 
the split-phase reduces the switching frequency required to 
reduce the output impedance of the PSC stage. This 
requirement can be achieved at a lower switching frequency 
limit when the split control diagram is used. Furthermore, the 
split-phase reduces the effect of the higher switching frequency 
in order to reduce the output impedance. This requirement can 
be instead achieved at a lower switching frequency.  

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