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A Review on Energy Efficient CMOS Digital Logic 

Branko L. Dokić 

University of Banja Luka 

Faculty of Electrical Engineering 

Patre 5, 78000 Banja Luka 

Bosnia and Herzegovina  

bdokic@etfbl.net 
 

 

Abstract— Autonomy of power supply used in portable devices 

directly depends on energy efficiency of digital logic. This means 

that digital systems, beside high processing power and very 

complex functionality, must also have very low power 

consumption. Power consumption depends on many factors: 

system architecture, technology, basic cells topology-speed, and 

accuracy of assigned tasks. In this paper, a review and 

comparison of CMOS topologies techniques and operating modes 

is given, as CMOS technology is expected to be the optimum 

choice in the near future. It is shown that there is a full analogy in 

the behavior of digital circuits in sub-threshold and strong 

inversion. Therefore, synthesis of digital circuits is the same for 

both strong and weak operating modes. Analysis of the influence 

of the technology, MOS transistor threshold voltage (Vt) and 

power supply voltage (Vdd) on digital circuit power consumption 

and speed for both operating modes is given. It is shown that 

optimal power consumption (minimum power consumption for 

given speed) depends on optimal choice of threshold, and power 

supply voltage. Multi Vdd /Vt techniques are analyzed as well. A 

review and analysis of alternative logical circuit's topologies – 

pass logic (PL), complementary pass logic (CPL), push-pull pass 

logic (PPL) and adiabatic logic – is also given. As shown, 

adiabatic logic is the optimum choice regarding energy efficiency. 

Keywords: topology; technology; power consumption; logic 

delay; CMOS; strong and weak inversion; static and dynamic 

characteristics; pass logic; adiabatic logic; PL; CPL; PPL; ECRL 

I. INTRODUCTION  

Designers of digital circuits are confronted with two often 
conflicting demands: how to achieve higher operating speeds 
and lower energy consumption. Usually, the same circuit 
family could not satisfy both demands at the same time, i.e. 
high-speed circuits have high level of consumption and vice 
versa. That’s how series of integrated circuits called low-power 
circuits or high-speed circuits were created. Optimally designed 
digital system includes a variety of different series of the same 
integrated circuits' family. 

Today, as the whole digital system is manufactured as a 
single integrated circuit, the designing problem is reduced to 
the choice of a design that can ensure maximum energy 
efficiency. That implies the design with minimum power 
consumption inside the specified frequency range or maximum 
operating speed for a given energy consumption level. The 
usage of low-power sources of power supply, which collect 
their primary energy from the environment, has increased 

lately. Thus, the art of design of low power circuits is brought 
down to the selection of optimal (intelligent) solutions that will 
reduce the speed of information processing as much as 
possible, without violating certain system characteristics. Such 
an optimal project implies the decomposition of the system 
architecture, good choice of the circuit topology that will 
provide the optimal synthesis of different functions in the 
defined architecture, and good choice of the circuit design 
technology. This requires the designer to be familiar with 
components, circuits and systems. Consumption of each system 
is determined using the following five guidelines of each 
project: given task, technology, circuit topology, operating 
speed and accuracy. Since these five guidelines can be placed 
on the fingers of one hand, they are known as “low-power 
hand” [1]. Therefore, optimization of energy consumption is a 
multidimensional problem that requires taking into 
consideration the level of consumption at each stage of the 
VLSI integrated circuit design. The biggest savings of 
electrical energy consumption (10 to 20 times), with least waste 
of time (at the level of a minute) is done in the early stages of 
designing, in which the project is presented as a set of abstract 
communication tasks [2]. The application of optimization 
techniques and consumption provides an estimation at each 
project stage, leading to optimal consumption project [3].  At 
lower levels of the design (transistor, deployment and 
connectivity), possible energy savings are significantly lower 
(10 to 20%), and time estimation can last for days, because the 
project is presented with all detail. Thus, it is necessary to 
process a very large amount of data [3]. CMOS digital circuits’ 
technology based on silicon will most likely be dominant for 
the next twenty years or more [4, 5, 6], with standard low 
power consumption, technology for reducing the transistor size 
to a scale of about ten nanometers and operating speed in the 
GHz domain. During the last ten years, more attention from 
researchers as well as manufacturer of integrated circuits is 
paid to digital CMOS circuits operating in the sub-threshold 
(weak inversion) regime. Supply voltage in this regime is lower 
than the threshold voltage Vt  of MOS transistors (Vdd<Vt) and 
is about a few hundred millivolts. Thanks to that fact, the 
dynamic consumption level is significantly reduced in regard to 
CMOS circuits operating in the strong inversion regime. Since 
the operating area in the sub-threshold regime is overlapped 
with the area of a disconnected transistors in strong inversion 
regime, current ratio in on and off the state has been 
significantly reduced. Consequently, CMOS circuit logic delay 



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in the sub-threshold regime is several orders of magnitude 
higher.  

Designers of CMOS digital devices, especially portable 
ones, have a challenging requirement: how to ensure high 
processing power and very complex functionality along with 
low power consumption. Certainly part of the solution is a 
proper choice of CMOS technology as well as weak and strong 
inversion regime operating areas.  

Although MOS transistor static characteristics in weak 
inversion and strong inversion regimes are functionally very 
different, it will be shown that there is an absolute analogy in 
the behavior and functional dependency of CMOS circuit 
parameters in those regimes. Thanks to that, design techniques 
of more complex CMOS circuits are the same in sub-threshold 
and strong inversion regime. This fact considerably facilitates 
designer's work of CMOS circuit in a sub-threshold regime and 
enables faster development.  

Optimal consumption generally does not mean minimal 
consumption. Minimal consumption and minimal logic delay 
are mutually opposite requirements. Taking into account only 
the minimization of consumption, a project with unacceptable 
logic delay could be delivered.   The consumption as well as 
the logic delay of CMOS circuit depends on MOS transistor 
threshold voltage Vt  and supply voltage Vdd . Because of that, 
one part of this paper is devoted to consumption optimization 
techniques in systems with multiple levels of Vt and Vdd . 

Specific part of this paper refers to the big toe of “low-
power hand”– topologies. Review of topologies of CMOS logic 
series that ensure low-power within the specified range of 
operating frequencies is given, which implies their use in both 
strong and weak inversion regimes.  

The analysis is based on simplified current-voltage models 
of MOS transistors and PSPICE software using parameters of 
180 nm technology.  

II. CMOS OPERATING IN THE WEAK INVERSION REGIME 

In essence, there are three areas of MOS transistor static 
characteristics [7]. Figure 1 shows the logarithmic dependence 
of nMOS transistor drain current as a function of gate-source 
voltage (Vgs), at a constant drain-source voltage (Vds) and 
source-substrate voltage (Vsb). In the literature, the smallest 
attention is paid to the medium (moderate) area which is mostly 
considered as a part of strong inversion threshold area [8, 9]. In 
digital circuits, it is assumed that Vgs>Vt, where Vt  is a MOS 
transistor’s threshold voltage, transistor is operating in strong 
inversion regime, and for Vgs<Vt in the sub-threshold (weak 
inversion) regime. Therefore, from today’s application point of 
view, it can be said that Vt is a gate-source voltage on a border 
between the weak and the strong inversion regime.  

It is a well-known fact that the Id (Vds, Vgs) characteristic in 
the strong inversion regime has two areas: non-saturated and 
saturated. In the non-saturated area, it holds that Id ~Vgs and 
Id~Vds

2
, while in saturated area Id ~ Vgs

2
 and Id ≠ f(Vds), that is Id 

≈const as a function of Vds. 

MOS transistor characteristics in the weak inversion regime 
are defined as follows: 

( )

( )

ϕ ϕ

ϕ

ϕ

ϕ

−

−

−


 − <

= 


>

/

0

0

1 , 3 ,  non-saturated area

, 3 ,  saturated area,                        1

gs t

t ds t

gs t

t

V V

n V

ds t

Dsub
V V

n

ds t

I e e V
I

I e V

                           

 

where  

( )µ ϕ= − 20 0 1ox t
W

I C n
L

                         (2) 

is a drain current on a border between weak and strong 
inversion. 

 

 

Fig. 1.  log Id characteristic as a function of Vgs  at a constant Vds and Vsb 

The meaning of the parameters in (1) and (2) are the 
following: µ0 is a mobility of major charge carriers (electrons 
and holes in nMOS to pMOS transistor), Cox = εox / tox is gate 
capacitance (εox  is a dielectric constant, tox is a thickness of the 
gate oxide), W and L are the width and length of the channel, 
respectively, φt=kT/q is a thermal potential (φt=26 mV at 
T=300K), where n=1+Cd /Cox≈1.5 is a gradient factor.  

For Vds>3φt, drain current is almost independent of the voltage 
Vds (Figure 2), so that the area analogous to strong inversion 
regime, can be treated as saturated area. In this area it holds 

~ gs
V

d
I e . For Vds<3φt, at Vgs=const., ds

V

d
eI ~ , transistor is in 

the non-saturated area.  

Thanks to the analogy in the field of MOS transistor 
characteristics, there is an appropriate analogy of operation and 
CMOS logic circuit characteristics [8]. Thus, for example, 
voltage and current static characteristics in the weak inversion 
regime (Figure 3) have the same shape as in the strong 
inversion regime. Even inverter threshold voltage VTsub is 



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obtained in the same way – equating of nMOS and pMOS drain 
currents in the saturated area of characteristics. 

 

Fig. 2.  Id(Vgs, Vds) in weak inversion regime 

It results with inverter threshold voltage VTsub in the sub-
threshold regime [8]:  

ϕ  
 = −
 
 

ln ,
2 2

ddsub t on

Tsub

op

V n I
V

I
                      (3) 

and maximal current from the voltage source: 

ϕ

−

=

/2

,

ddsub t

t

V V

nop

ddMsub on

on

I
I I e

I
                       (4) 

where 

ϕ < < = =3
t ddsub t tn tp
V V V V                         (5) 

is a supply voltage, Vtn and Vtp threshold voltages, and Ion and 
Iop currents on the border between weak and strong inversion of 
nMOS and pMOS transistors, respectively. For a symmetric 
inverter (Ion=Iop),  threshold voltage is, just like in strong 
inversion regime, VTsub=Vddsub/2. 

Minimal supply voltage, according to [7] is Vddmin=3φt=78 
mV. For Vddsub>3φt , the Id(Vgs, Vds) characteristic has both 
saturated and non-saturated areas, which is necessary for 
satisfying the quality of digital circuit transfer characteristic 
Vo(Vi). However, logic circuits can operate even at Vdd<3φt. 
Thus, for example, some authors [9] state constraints Vdd>57 
mV, while others [10] claim that Vdd>48 mV. 

As in strong inversion regime, threshold voltage VTsub and 
maximal current IddMsub in the sub-threshold regime both 
depend on nMOS and pMOS transistor geometry (Figure 3), 
except that IddMsub~(Wn/Wp)

-1/2 
and VTsub ~ln(Wn /Wp), where Wn 

and Wp are the channel widths of nMOS and pMOS transistors, 
respectively. 

           vin1

50mV 100mV 150mV 200mV 250mV

ID(Mn)

0A

50pA

100pA

150pA

SEL>>

V(2)

0V

100mV

200mV

300mV

 

Fig. 3.  (a) PSPICE voltage and (b) current transfer characteristic of 
CMOS inverter in the sub-threshold regime, for channel width ratios Wp 
/Wn={1, 8/3, 5, 9} at equal channel length (Ln=Lp) and Vddsub = 300 mV 

Considering the behavior analogy and CMOS inverter 
characteristics in the weak and strong inversion regime, there is 
an analogy even at synthesis of more complex circuits. In both 
regimes, more complex digital circuits consist of dual nMOS 
and pMOS transistor networks (Figure 4). Duality implies that 
a serial connection of nMOS transistors is corresponding to a 
parallel connection of pMOS transistors and vice versa. 

 

Fig. 4.  Topology of the circuit with logical function +ab c  consisted of 
dual networks: +ab c  (nMOS) and +( )a b c  (pMOS) 

In both regimes, logic circuit transfer characteristic depends 
on the number of inputs and number of active inputs [8]. Figure 
5a shows the transfer characteristics of NOR3 logic circuit with 
all inputs activated, and when the activated input is the one 
applied to the gate of a pMOS transistor whose source is 
connected on a power-supply  line Vdd .  

     1 

     5 

     9 

     

8/3 

     9 
     

8/3 

     5 

     1 

     

a) 

     

b) 

VTsub 

IddMsub 



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0.05 0.1 0.15 0.2 0.25
0

0.05

0.1

0.15

0.2

0.25

0.3

Vin [V]

V
o
u
t 
[V
]

 

0.05 0.1 0.15 0.2 0.25
0

0.05

0.1

0.15

0.2

0.25

0.3

Vin [V]

V
o
u
t 
[V

]

 

Fig. 5.  PSPICE transfer characteristics of  (a) NOR3 and (b) NAND2  
circuits in the weak inversion regime, with all inputs activated, and when 

the activated input is the one applied on the gate of a serial transistor 

whose source connected on power supply line. 

In NAND circuits, the highest threshold voltage is obtained 
when all inputs are active, and the lowest when the active input 
is only the one applied to the gate of nMOS transistors, whose 
source is connected to the ground (Figure 5b). Optimal 
transistor geometry of m-input NAND and NOR circuits is the 
same in both regimes and is defined as follows [12]: 

µ

µ

µ

µ

=

=

/

/

/ 1
.

/

pn n

p p n

pn n

p p n

W L
m

W L

W L

W L m

                    (6) 

III. CMOS CIRCUIT POWER CONSUMPTION 

Electric power consumption consists of two components: 
static and dynamic 

D DS DD
P P P= + .                              (7) 

Static consumption is a result of existing MOS transistor 
currents in static states and is defined as: 

,
DS S dd
P I V=                                 (8) 

where IS  represents the static current in total. 

There are four main sources of static current in CMOS 
circuits: 

• Tunneling current through the gate (Ig), 

• Sub-threshold drain current (Idsub), 

• Inverse polarized p-n junction current (IDSS), 

• Hot charge carrier injection gate current (IH). 

The first three components have dominant influence on 
CMOS circuit static consumption level.  

Scaling of the dimensions of MOS transistors decreases 
oxide thickness below the gate (tox). Therefore, the electric field 
through gate oxide increases, which leads to the tunneling 
effect of charge carriers from gate to substrate or from substrate 
to gate. The gate current has four components: gate-channel 
(Igc), gate-drain (Igd), gate-source (Igs) and gate-base (Igb) (Fig. 
6). The total gate current is:  

.
g gd gb gs gc
I I I I I= + + +                       (9) 

VDD

Igd

Igb

Igc

Igs

+VDD

Vo=0

+VDD

Vo=VDD

IsgIbg

Icg
Idg

 

Fig. 6.  Gate leakage currents of (a) nMOS and (b) pMOS transistor  

Gate currents depend on supply voltage Vdd  and on the 
employed technology (Table I) [11]. Thus, for example, when 
increasing the supply voltage level from Vdd=0.2 V to Vdd=1.2 
V, the gate current increases from Ig ≈1.2 nA to Ig≈1.7 µA. The 
increase ratio is approximately 1.4·10

3
 times. When reducing 

the transistor dimensions, gate current increases as well. For 
nMOS transistor, according to Table I, that increase for 45 nm 
in regard to 65 nm CMOS technology, depending on Vdd, is 
approximately 7 (at Vdd=1.2 V) to 14 (at Vdd=0.2 V) times.  

TABLE I.  NMOS TRANSISTOR GATE CURRENT AS A FUNCTION OF SUPPLY 
VOLTAGE FOR TWO DIFFERENT TECHNOLOGIES 

Ig 
Vdd [V] 

45 nm tech. 65 nm tech. 

0.2 1.1996 nA 85.506 pA 

0.4 14.258 nA 1.2376 pA 

0.6 66.954 nA 6.5488 nA 

0.8 225.97 nA 25.244 nA 

1.0 647.38 nA 82.378 nA 

1.2 1.6811 µA 243.21 nA 

 

The nMOS transistor leakage current is greater than in 
pMOS, because the probability of holes tunneling is greater 
than the probability of electrons tunneling through the gate 
oxide. That increase, depending on supply voltage is 40 times 
[11]. 

The sub-threshold leakage current is a cutoff transistor 
(Vgs=0) drain to source current (Figure 7) and it is given as: 

NIm: 

NILIm: 

a) 

b) 

V
i

V
i

V
i

“1”

V
i



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dd t

t

V V

n

ddsub o
I I e

η
ϕ
−

=          (10) 

where η is the DIBL (Drain–Induced Barrier Lowering) factor 
[9]. 

This current values depend on the supply voltage, the 
dimensions of elements (technology) and the temperature. In 
Table II, comparative values of gate current and sub-threshold 
drain current as a function of supply voltage Vdd and 
temperature are given, for 45 nm technology. It is evident that 
the dependency of Ig on Vdd and in function of temperature 
dependency of Idsub is more expressed. On the other hand, at 
temperature of 25°C it holds Vdd ≤ 0.6 V, Ig<Idsub, while for Vdd 
>0.6 V, Ig >Idsub. Thus, for example,  for Vdd =1.2 V holds that 
Ig≈13Idsub. 

VDD

+VDD

0

+VDD

VDD

Idnsub

Idpsub

 

Fig. 7.  Sub-threshold currents of (a) nMOS and (b) pMOS transistors in 
CMOS inverter 

TABLE II.  GATE AND SUB-THRESHOLD DRAIN CURRENT OF NMOS TRANSISTOR 
AS A FUNCTION OF VDD  AND TEMPERATURE  

Gate current Ig [nA] 
Sub-threshold current   

Idsub [µA] Vdd [V] 

25°C 110°C 25°C 110°C 

0.2 1.1996 1.2689 40.999 0.88086 

0.4 14.258 15.776 56.437 1.1586 

0.6 66.954 75.437 72.47 1.4401 

0.8 225.97 256.33 89.397 1.7334 

1.0 647.38 736.31 107.42 2.0428 

1.2 1681.1 1914.3 127.12 2.3785 

 

Inverse saturation current Idss of the p-n junction of a 
turned off transistor depends on the p-n junction surface and 
temperature. For 0.25 µm technology, it is between 10 and 100 
pA/µm

2 
at a 25°C temperature per area unit. In nanometer 

technologies, this current is less than Ig and Idsub, and can be 
ignored. 

Dynamic consumption consists of two components: 
switching consumption and transition (short-circuits) 
consumption. Switching consumption is the result of charging 
and discharging of a load capacitor and in both regimes is 
defined as: 

= = 2 ,
d ddsub L dd
P P C V f                         (11) 

where CL is the effective output parasite capacitance, and  f  
is the switching state frequency of the CMOS logic circuit. 

Transition consumption occurs due to conduction of both 
transistors or transistor networks (nMOS or pMOS) during 
switching states (transition area) (Figure 3). In strong inversion 
regime, transition consumption is defined with [12] and is: 

( )( )= − +1 2 ,
3

dp ddM DD t r f
P I V V t t f             (12) 

where 

( )
µ

µ
µ

−
=

 
 +
 
 

2

2

2

2
/

1
/

DD tox n

ddM n

n
n n n

p p p

V VC W
I

L
W L

W L

       (13) 

is the maximal voltage supply current in transition area, and tr 
and tf  are the rise time and fall time input signals. 

In sub-threshold regime, dissipation power of transition is 
defined with [8] : 

( )ϕ= +2 ,dpsub t ddMsub r fP n I t t f                 (14) 
where IddMsub is defined with (4), and f  is an input signal 
frequency. 

Usually, dynamic dissipation power is calculated 
(estimated) in regard to clock frequency. Namely, most number 
of logic circuits does not change their state during every cycle 
of clock signal. Therefore, expressions for dynamic 
consumption have to be multiplied with activity factor α≤1, 
regarding to clock frequency, so that: 

( )( )

( )

α α

α α ϕ

= + − +

= + +

2

2

,
3

2 .

ddM

dd c L dd c dd t r f

ddsub c L ddsub c t ddMsub r f

I
P f C V f V V t t

P f C V f n I t t

     (15) 

Product αfc, where fc  is the clock frequency, is the activity 
of the circuit indicating the number of state changes. Mostly, 
activity factor is α<0.5. It is determined empirically that static 
CMOS digital circuits have α ≈ 0.1 [13]. 

IV. LOW POWER DESIGN TECHNIQUES 

Optimal project implies a compromise between operating 
speed and low power, which all design levels take into account 
[2]. In this section, we will speak about the optimal project 
considering the choice of transistor threshold voltage Vt and 
system power supply voltage Vdd. 

In the previous paragraph, it was shown that both static and 
dynamic consumptions are decreased with the reduce of Vdd. 
Dynamic switching consumption in both regimes is 
proportional to Vdd

2
. Transition consumption in the strong 

inversion regime is Pdp~(Vdd - Vt)
3
, and in sub-threshold regime 

/2
~ dd t

V V

dpsub
P e

−
. Static currents, depends on supply voltage as 

well (Tables I and II), so that PS ~Vdd
n
, where n is usually in the 

range of 1<n<4.  



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Logic delay also depends on Vdd  and Vt. Namely, in the 
strong inversion regime, capacitor charging/discharging current 
is Id~(Vdd - Vt)

2
 in the saturated area, and Id ~ (Vdd - Vt)Vo in the 

non-saturated area (Figure 8). In the sub-threshold regime that 

current is 
( )

~ t dddd t
V VV V

dsub
I e e

− −−
= (Figure 8). Thus, reduction 

of Vdd  increases the logic delay in both regimes. In order to 
maintain the logic delay at lower Vdd , threshold voltage Vt 
should be reduced. Over a long period of time, CMOS digital 
circuit's performance increasing scenario was conducted in the 
process of reduction of element's dimensions, by lowering Vdd 
and Vt. However, reduction of Vt below 200 mV leads to 
exponential increase of sub-threshold current as shown in (4). 
This may cause the static consumption to be higher than the 
dynamic. Consequently, it can be said that the reduction of 
threshold voltage is limited to approximately Vtmin=200 mV. 

 

 

Fig. 8.  Discharge currents of capacitor CL in the strong and weak 
inversion regime 

V. MULTI VDD /VT OPTIMIZATION TECHNIQUES 

A compromise between low power and sufficient speed can 
be achieved using transistors with different threshold voltages. 
This technique is known as the multi-threshold technique or 
MTCMOS [14, 15]. Critical signal path is designed using logic 
with lower threshold voltages. Transistors with higher Vt  are 
used where delay is not critical. The second approach with the 
MTCMOS technique is based on the so-called gated voltage 
supply (Figure 9). In static states, relatively in time of logic 
inactivity (Standby Mode), voltage supply is turned off using 
transistors with high threshold voltage. Thus, the small sub-
threshold current is secured, along with low static dissipation. 
Logic block transistors are designed with low Vt  so that the 
needed speed is preserved.  

Using control “wake up” signal SL   (Sleep), over a pMOS 
transistor with high Vt, the connection between true Vdd and 
virtual power supply VddV is controlled. While Mp is turned off, 
capacitor CB maintains the virtual power supply of the logic 
block. 

Reduction of the leakage currents of inactive components 
can be achieved using nMOS transistors between the logic 
block and the ground, or with pMOS and nMOS transistors at 

the same time [15]. The state of the pMOS transistors is then 

controlled with the SL  signal, and of the nMOS with the SL 

signal.  

The ratio between the consumption and the speed of data 
processing is optimized using several power supplies in the 
same design. Logic circuits over critical delay paths are 
supplied with higher VddH, and circuits whose delay is not 
critical with lower voltage VddL (Figure 10). The number of 
voltage levels can be greater, but it turns out that the largest 
effect is achieved using two power supplies [16]. It should be 
noted that the transition from logic with VddL to logic with VddH 
power supply is achieved using logic voltage level converters. 
This as well limits the number of power supply levels. 

 

 

Fig. 9.  MTCMOS block diagram with gated voltage supply 

 
Fig. 10.  Two registers connected with different delay paths 

Often in the same digital system, techniques with several 
power supplies and several threshold voltages have been used – 
multi Vdd /Vt techniques [16, 17]. Optimal operating point 
(Vddopt, Vtopt) is determined on Vdd -Vt plane with constant power 
consumption lines (equi-power) and speed lines (equi-speed) 
(Fig. 11). These lines depend on technological process and 
project architecture. 

The choice of the optimal (Vddopt,Vtopt) pair depends on 
technological process constraints. Let say that those constraints 
are: Vdd=3.3V±10% and Vt=0.55 V±0.1. The area of allowed 
values for these limitations is shown in Figure 11, with a larger 
rectangle. For all values of Vdd and Vt inside this rectangle, 
system fulfills all given specifications. In A corner, system will 
have the highest delay, and in B corner the highest energy 
consumption. Constant speed and constant consumption lines 
are normalized at points A and B by normalization factors ks 
and kp, respectively. Based on that, we determine the influence 



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of position changes and the rectangle size in Vdd-Vt plane, onto 
consumption and system speed. For example, smaller rectangle 
on Figure 11 is defined with constraints Vdd=2.1 V±5% and 
Vt=0.18 V±0.05, and consumption is 60% (kp=0.4) lower for 
the same operating speed (ks=1). 

 

Fig. 11.  Vdd-Vt plain with constant power consumption and delay lines 

From all possible Vdd-Vt combinations that meet given time 
constraints, only one combination (Vddopt, Vtopt) guarantees 
minimal consumption. Shuster et. al. [18] proposed an 
equation, based on the transistor alpha model, for the 
calculation of total system consumption with the optimal 
(Vddopt, Vtopt) pair. Nevertheless, it should be stated that the 
continual change of Vddopt and Vtopt is unpractical. Designers are 
mostly allowed to choose between several discrete (Vddopt, Vtopt) 
values. By applying the multi Vdd  technique, dynamic 
consumption can be reduced from 10%, up to 50%, whereas by 
applying the multi Vt technique, static consumption can be 
reduced for 50%, even up to 80% [3]. In [16], the optimal ratio 
between Vdd and Vt is given (Table III). 

TABLE III.  OPTIMAL RATIO OF VDD AND VT  CONSIDERING CONSUMPTION  

Vddi, i=1,2,3,4,  Vt=const 

(Vdd1,Vdd2): 
2

1 1

0.5 0.5dd t

dd dd

V V

V V
= +

 

(Vdd1,Vdd2, Vdd3): 
2 3

1 2 1

0.6 0.4dd dd t

dd dd dd

V V V

V V V
= = +

 

(Vdd1,Vdd2, Vdd3, Vdd4): 
2 3 4

1 2 3 1

0.7 0.3dd dd dd t

dd dd dd dd

V V V V

V V V V
= = = +

 

Vti, i=1,2,3,4,  Vdd=const 

(Vt1,Vt2): Vt2=0.1Vdd+Vt1 

(Vt1,Vt2, Vt3): 
Vt2=0.06Vdd+Vt1 
Vt3=0.07Vdd+Vt2 

(Vt1,Vt2, Vt3, Vt4): 
Vt2=0.04Vdd+Vt1 

Vt3=0.05Vdd+Vt2 
Vt4=0.06Vdd+Vt3 

VI. CMOS LOW POWER TOPOLOGIES 

Standard CMOS combinational logic demands a CMOS 
transistor pair per every input. However, various alternative 
topologies with the lower number of transistors have been 
developed. Besides, the increase of scale of function integration 
in VLSI integrated circuit, has led to a reduce of consumption 
or increase of speed at the same consumption level.  

Among the first alternative CMOS digital logics is the 
transmission-gate logic. Unlike standard logic where the basic 
cell is the inverter, in transmission-gate logic, the basic cell is 
the transmission gate. While in standard logic circuits, output 
signals are separated from the inputs, here the input signal is 
transferred to the output via the transfer gate. Figure 12 shows 
a 2/1 multiplexer (2/1 MUX) in transmission-gate logic. Since 
the complementary signals are needed for transmission gate 
control, inverters are integral part of the network as well. The 
2/1 MUX in Figure 12 consists of only three CMOS transistor 
pairs, while standard logic needs seven pairs. 

 

 

Fig. 12.  MUX 2/1 in transmission-gate logic 

Transmission gate logic can be additionally simplified by 

applying signals b  and b  to the inverter power line as in the 
example of XOR and XNOR circuit synthesis shown in Figure 
13. The inverters with the (Mn, Mp) transistor pair are powered 

by b   and b signals. 

In the synthesis of logical functions in transmission-gate 
logic, it must be taken into account that between the output and 
at least one input, a contour of small resistance exists. 
Otherwise, output would be in the state of high impedance with 
the undefined logic level. 

  

 

Fig. 13.    (a) XOR  and (b) XNOR circuits  

As a transmission gate, instead of a CMOS pair, only 
nMOS transistors can be used (Fig. 14). The number of 
transistors is halved and the static consumption and the parasite 

V
t 
(V

) 



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capacitance are reduced as well, which significantly increases 
the scale of function integration in a VLSI circuit.  

 

d0

d1

d2

d3

a a b b VDD

z z

dd

 

Fig. 14.  MUX 4/1 in pass-transistor  nMOS logic with true and 
complementary output 

The problem with the nMOS pass-transistor logic is that the 
maximal voltage variation on one nMOS transistor is Vdd-Vtn 
and lower, for threshold voltage Vtn comparing to the CMOS 
transmission gate. That limits the number of serial transistors. 
Therefore, nMOS transistors with very low (NTL-Aon 
Threshold Logic) or zero threshold voltage (ZTT-Zero 
Threshold Logic) have been used. The problem of mentioned 
logics lies in the low noise immunity.  

Reduction of logic amplitude in nMOS transmission-gate 
logic is especially a problem when nMOS network ends with 
an inverter. That problem can be solved using a pMOS 
transistor Mp as shown in Figure 16. When z  = 0, Mp is on 
and maintains the value of nMOS network output voltage at 
Vdd. 

Low threshold transistors are used in the so-called  CPL 
(Complementary   Pass-Transistor Logic). This logic consists 
of two nMOS transistor networks with common control and 
complementary transfer signals (Figure 15). 

PPL (Push-pull Pass-transistor Logic) [19] also have two 
transistor networks: one nMOS and the other pMOS (Figure 
16). The control signals are common, and inputs are 
complementary. Output logic levels have been restored to Vdd 
and 0 by transistors Mp and Mn, respectively. 

Table IV shows full adder comparative characteristics using 
different logics, implemented in 0.8 µm technology at Vdd=3.3 
V. Although pMOS transistors are slower than nMOS, logic 
delay of PPL is approximately like CPL, but the consumption 
is significantly lower. 

TABLE IV.  FULL ADDER COMPARATIVE CHARACTERISTICS 

Parameter CMOS CPL PPL 

Logic delay [ns] 1.57 0.84 0.83 

Cons. [mW/100Hz] 1.90 1.33 0.42 
P·td (normalized) 1 0.38 0.12 

 

 

a

b

b

b

ab

ab

a
b

a
a

b

ab

ab

b

a+b

a+b

a+b

a+b

a

b

a b

a b

a
b

a
a

b

a

a

a b

a b

a)

b)

c)

a
b

a

b

a

b

b

a

b

b

b

 

Fig. 15.  AND/NAND (a), OR/NOR (b) i XOR/XNOR (c) logic circuits in 
CPL 

 

Fig. 16.  PPL block sheme 

VII. ADIABATIC LOGIC 

The Term “adiabatic” describes thermodynamic processes 
in which the amount of heat remains constant (there is no 
exchange of energy with the environment). Adiabatic logic in 
the ideal sense, designate digital circuits without loss 
(dissipation) of electrical energy. In practice, it denotes the 
logic with minimal consumption of electrical energy during the 
switching of states. Adiabatic switching state shifting is a 
charge/discharge mechanism which returns accumulated 



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energy to the source inside the load capacitor using the 
dynamic power supply. Dynamic power supply or clocked 
power has a very important role in adiabatic logic, because 
beside power supply, it provides energy recovery. 

Nowadays, there are many techniques of adiabatic logic 
[20-25]. Energy recovery process will be explained on the 
example of ECRL (Efficient Charge Recovery Logic) inverter 
(Figure 17). Power supply PC is with trapezoidal pulses. 

PC

Mp1 Mp2

Mn1 Mn2

C
L

C
L

Q Q

a a

0
Vdd

Accumulation

(chargingC
L
)

Energy 

recovery

(discharging C
L
)

 

Fig. 17.  ECRL inverter scheme 

In the initial state holds a=1, and the Mn1 is conducting 
(Q=0). While PC rises from 0 to Vdd, over conductive transistor 

Mp2 the output Q  follows the variation of PC. When PC 

reaches the Vdd value, then it holds Q =1, and Q =0 and those 

conditions are valid logic states at inputs of next stage. During 
the fall of PC from Vdd to zero, the right capacitor CL 
discharges over the conductive Mp2 and PC, and therefore 
recovers accumulated energy to the PC supply. 

More complex ECRL circuits have two complementary 
nMOS transistor networks with complementary excitations 
(Figure 18), instead of Mn1 and Mn2 transistors. Complementary 
networks are obtained by complementing input signals and 
switching of logic operators as a function of  fn  nMOS 
network. 

For example, fn   2/1 multiplexer function is 

( )
n

f sa sb= +  and the function of complementary network 
is ( )( )

n
f s a s a= + +  (Figure 18b). 

Other adiabatic topologies should be mentioned as well: 
PAL (Pass-transistor Adiabatic Logic) [21], CPAL 
(Complementary PAL), PFAL (Positive Feedback Adiabatic 
Logic) [20] etc. Reduced energy consumption comparing to 
standard CMOS logic is around 50 to 90%. 

 

 

s b

s b

{ fn } network

b a

s s

{ fn } network

b)
 

Fig. 18.  (a) Block scheme of complex ECRL circuit  (b) with 
n

f  and nf  

MUX2/1 network  

VIII. CONCLUSION 

To enable the design of energy-efficient digital systems, 
designers must take into account the electrical energy 
consumption through all design phases, from functional 
description to transistor level. The biggest energy saving (10 to 
20 times) with the least time needed for consumption analysis 
is acquired on the system design level. In the sub-threshold 
regime, consumption is several orders of magnitude lower, but 
operating speed is lowered by nearly the same amount in 
comparison to the strong inversion regime. Rescaling of 
transistor dimensions increases gate current Ig which is very 
dependent on power supply. Multi Vt /Vdd design techniques 
provide the reduction of consumption to a scale of about ten 
percent at the same operating speed. Digital systems with two 
power supplies and/or two threshold voltages are optimal as 
well. Using two threshold voltages, static consumption can be 
reduced up to 80%. Alternative topologies provide larger scale 
of function integration per single VLSI circuit, lower 
consumption level and higher-speed rate. The transfer logic has 
the widest application in VLSI digital circuit design whereas 
adiabatic logic ensures the greatest energy saving (up to 90%). 

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