Microsoft Word - ETASR_V11_N2_pp7054-7059 Engineering, Technology & Applied Science Research Vol. 11, No. 2, 2021, 7054-7059 7054 www.etasr.com Vu et al.: A Novel Modeling and Control Design of the Current-Fed Dual Active Bridge Converter … A Novel Modeling and Control Design of the Current-Fed Dual Active Bridge Converter under DPDPS Modulation Phuong Vu School of Electrical Engineering Hanoi University of Science and Technology Hanoi, Vietnam phuong.vuhoang@hust.edu.vn Do Tuan Anh School of Electrical Engineering Hanoi University of Science and Technology Hanoi, Vietnam tuananhdo.hust@gmail.com Hoang Duc Chinh School of Electrical Engineering Hanoi University of Science and Technology Hanoi, Vietnam chinh.hoangduc@hust.edu.vn Abstract-This paper proposes a novel control design for a Current-Fed Dual Active Bridge (CFDAB) converter in boost mode. The Double PWM plus Double Phase Shifted (DPDPS) modulation is applied to the converter due to its considerable merits. A small-signal model is developed to control the output voltage stably in boost mode. Simulations of the control design for the CFDAB converter were conducted to verify the proposed model. The results show that the system can achieve high performance, not only in the dynamic response but also in the steady-state. Keywords-Current-Fed Dual Active Brigde (CFDAB) converter; small-signal model; Double PWM plus Double Phase Shifted (DPDPS) modulation I. INTRODUCTION Nowadays, the growth in renewable power systems urges researchers and engineers to solve the problems of managing integrated storages and exchange powers to enhance overall system efficiency. In order to connect the battery at low voltage to the DC link at high voltage in a storage system, the utilized DC/DC converter needs to have a high gain voltage factor and an ability of bidirectional transferring power. The DC/DC converters can be classified as isolated and non-isolated. Between these two, the isolated DC/DC converter is highly recommended for its high reliability. It is able to eliminate current leakage in the system. This undesired current is the cause of EMI, additional loss, and unsafe installation and operation [1]. Another advantage of the isolated DC/DC converter is that the flexible gain ratio can be obtained by using a high frequency transformer [2, 3]. The Dual Active Bridge (DAB) converter belongs to the isolated DC/DC type and is well-known for its advantages of high frequency operating ability, inherit zero voltage switching, and bidirectional power flow [4-6]. The structure of the DAB can have modified flexibly with different power sources [7-8]. The DAB converter is divided into two categories: Voltage-Fed (VFDAB) and Current-Fed (CFDAB). When using the VFDAB structure in a variety of applications [9-11], the voltage source is directly supplied to the converter, which produces high current ripple and becomes large and costly. Besides, the VFDAB needs a bulky capacitor in series-connection with the primary coil to avoid the flux saturation of the transformer [11]. Therefore, the CFDAB structure is used to deal with these problems, the input interleave boost inductors in CFDAB help to decrease the current ripple significantly, and ZVS can be achieved for all switches over a wide range of load [9-12]. On the other hand, a small-signal model needs to be built for the accurately controlling problem. Naturally clamped CFDAB modeling structure has been introduced in [13, 14]. Besides, a state-space model under SPSPWM modulation for interleaved boost CFDAB structure is mentioned in [15]. In the current research, DPDPS modulation technique in comparison with SPSPWM modulation [9] is applied, and a small-signal model to regulate the output voltage is built up in boost mode. The simulation results show the effectiveness of the proposed method. II. RESEARCH METHOD A. Operation Principles and Control Structure 1) Operation Principles The applied structure of CFDAB converter in this research is presented in Figure 1, which consists of 2 main parts: the interleaved boost part and the dual active full-bridge part. In the interleaved boost part, two DC inductors are considered as two current sources. The inductor Ldc1 is combined with the left leg containing the switch pair Q1, Q1a to create the first boost converter, while the right leg containing the Q2, Q2a switch pair is combined with the inductor Ldc2 to create the second boost converter. These boost converters are 180˚ phase-shifted in order to compose an interleaved boost part, in which the boost voltage is kept by the clamp capacitor Cc. On the other hand, the dual active full-bridge part consists of two H-bridge modules in two sides of an isolated high frequency transformer with the turn ratio of N: 1. Corresponding author: Phuong Vu Engineering, Technology & Applied Science Research Vol. 11, No. 2, 2021, 7054-7059 7055 www.etasr.com Vu et al.: A Novel Modeling and Control Design of the Current-Fed Dual Active Bridge Converter … R Fig. 1. Structure of the CFDAB converter. The voltages of the clamp capacitor and the output capacitor are assumed as the Low-Voltage Side (LVS) and High-Voltage Side (HVS). The bidirectional transfer power between the LVS, the HVS, and the power flow are determined by the phase shifted angle. The AC inductor Lr, which is the sum of the primary-referred transformer leakage inductor, which can be considered as a power link between the two sides of the converter. 2) Modulation Strategy Due to the high amount of switch devices and inductors, the modulation strategy for the converter needs to be considered before designing the control loop. To handle the voltage ratio variation problems and to minimize the conduction loss in power transfer stages, the PWM plus Phase Shifted (PPS) is introduced while the duty cycle for HVS switches is equal to 50% and the duty ratio for the main LVS switches Q1, Q2 is a variable D. However, in the non-power transfer stage of PPS, the circulation loss is significant with high leak current spike. An additional phase shifted in Double PWM plus Double Phase Shifted (DPDPS) method [9], which equals to (2D 1) / 2 s T− × , is applied to eliminate the leak current spike. Figure 2 illustrates the modulation rule of the CFDAB converter, where the phase shifted between Q1 – Q2, Q2 – S1 and S1 – S4 are 180˚, ϕ and S ϕ respectively. The value of E ϕ determines the power flow and direction, where 0 E ϕ > represents the operation boost mode with power flow from LVS to HVS and vice versa. By utilizing DPDPS modulation, 8 operation modes in one switching period along with leakage current, the switching LVS voltage and the transformer voltage waveform vcd are displayed in Figure 3 [9]. Phase shifted Sawtooth Phase shifted D 0.5 Phase shifted Fig. 2. DPDPS modulation technique for the CFDAB converter. ab v cd v Lr i 1 Q 1a Q 1 Q 2 Q 2a Q 2a Q 3 S 3 S 1 S 2 S 2 S 4 S 0 π 2π Mode I Mode II Mode III Mode IV Mode V Mode VI Mode VII Mode VIII tω tω tω ϕ 2 Dπ (1 )2D π− cV Fig. 3. Pulse patterns, transformer voltage, and leakage current waveforms. 3) Control Structure For CFDAB converter structure, the transfer power is related to the clamp voltage Vc and the phase shifted Eϕ between the two H-bridges. Therefore, the control structure in boost mode has to control the voltage of the clamp capacitor and the output capacitor simultaneously. There are two pairs of control variables: Vc−d and Vo−ϕ , as presented in Figure 4. Lead-lag Duty ratio Primary Phase shift Pri and Sec Q1 Q2a S1 S4 Battery discharge D PI Vc-Control Fig. 4. Control structure in boost mode. B. Small Signal Modeling It is required to determine the transfer functions of the two pairs of control variables mentioned above so that the control scheme in Figure 4 can be implemented. The transfer function perturbations between clamp voltage ˆ c v and duty ratio d̂ is depicted in (1) [9]: Engineering, Technology & Applied Science Research Vol. 11, No. 2, 2021, 7054-7059 7056 www.etasr.com Vu et al.: A Novel Modeling and Control Design of the Current-Fed Dual Active Bridge Converter … ( )1 2 _ 2 2ˆ ˆ 2 (1 ) 2 c c r L Lc v d r d V L I Iv G d L C s D ϕ ω ϕ ω ϕ π − + = = + − − (1) In this paper, the small signal model along with the closed loop controller is proposed to regulate the output voltage of the converter under DPDPS modulation. In the secondary side, the output capacitor is charged and discharged in power transfer and non-power transfer stage respectively. From the switching sequence in Figure 3, the time interval of each switching mode is given by: 1 3 5 7 4 8 2 6 2 1 , 2 1 2 2 d d d d d d d d d d ϕ π ϕ π  = = = =  = = −  −  = = −  (2) The relationship between small signals of variables is presented in Table I for 8 modes in one DPDPS switching period. The inductors and capacitors are considered as ideal, i.e. the internal resistors are neglected. The continuous-time equation of output voltage is defined as: ( ) ( ) ( ) ( ) 4 8 1 2 3 4 5 6 7 8 5 5 1 1 o o o vdv c C N d d dt Lr v d d d d d d d d R v vc c Nd Nd L Lr r ϕ ω π θ ϕ θ ϕ ω ω = − + − + + − − + + − + − + − − (3) Using the average model: 7 2 , 2 c c d v v ϕ θ π= + = , 3 (2 1) 2 d ϕ θ π= − + we can obtain: ( ) ( ) ( ) 0 0 4 8 1 5 0 1 2 3 4 5 6 7 8 2 c c r r v vdv C N d d N d d dt L L v d d d d d d d d R ϕ ϕ ω ω = + + + + − + + − − + + − (4) Replacing (2) to (4) we get: ( ) 2 0 0 0 4 3 2 (1 ) 2 c r dv v v C d N d dt R L ϕ ϕ π ω  − = − + + −    (5) Using the perturbations of duty ratio, phase-shifted angle output voltage, and clamp voltage we have: ( ) 00 2 ˆ ˆ( ) ( )ˆ4( ) 3 ˆˆ( ) ˆˆ2( )(1 ( ) 2 o o o c c r d V v V v C D d dt R V v N D d L ϕ ϕ π ω + + = + − +   +− Φ+ + + Φ+ − +    Discarding the steady-state value and the second order perturbations and assuming that ˆ ˆ 0 Cc d v= = we get: ( ) 2 0 0 0 4 3 2 (1 ) 2 c r dv v v C d N d dt R L ϕ ϕ π ω  − = − + + −    (7) By Laplace transformation, the transfer function from ô v to ϕ̂ in the frequency domain can be expressed as: ( )_ 0 (2 2 ) 4 3o c v r r NRV D A G RL C s L D Bs C ϕ π ω ω Φ − − = = − − + (8) TABLE I. SMALL SIGNAL MODEL IN EACH SWITCHING MODE Mode Continuous- time equations Mode I [0, φ] ( )0 00 , c Ts Lr Lr r vdv v C Ni i dt R L θ ϕ ω = − − = − Mode II [ ,(2 1) ]dϕ π− 0 0 0 , 0 Lr dv v C i dt R = = Mode III ( ) ( )2 1 , 2 1d dπ π ϕ− − +   ( )0 00 , 2 1 c Ts Lr r vdv v C i d dt R L θ π ω = = − −   Mode IV ( )2 1 ,d π ϕ π− +   0 0 0 , c Ts Lr Lr r vdv v C Ni i dt R L ϕ ω = − + = Mode V [ ],π π ϕ+ ( ) 0 0 0 , c Ts Lr Lr r vdv v C Ni i dt R L π θ ϕ ω = − + = − + Mode VI [ ],2dπ ϕ π+ 0 0 0 , 0 Lr dv v C i dt R = = Mode VII [ ]2 ,2d dπ π ϕ+ [ ] 0 0 0 , 2 c Ts Lr r vdv v C i d dt R L θ π ω = = − − Mode VIII [ ]2 ,2dπ ϕ π+ 0 0 0 , c Ts Lr Lr r vdv v C Ni i dt R L ϕ ω = − − = − C. Simulation Verification The control design with the proposed method is firstly verified by simulation in Matlab/Simulink (Figure 5). The specifications of the converter are given in Table II and the transfer function in frequency domain between ô v and ϕ̂ is turned into: 4 _ ˆ 1.643 10 ˆ 0.3213 4.7 o vo v A G Bs C s ϕ ϕ × = = = + + (9) A PI controller is applied to regulate the output voltage: 1 (1 ) c p G K Tis = + (10) where Ti is equal to the pole of _ovG ϕ : 0.068 i B T C = = . The output voltage close loop transfer can be written as: 1 1 k k G T s = + (11) Engineering, Technology & Applied Science Research Vol. 11, No. 2, 2021, 7054-7059 7057 www.etasr.com Vu et al.: A Novel Modeling and Control Design of the Current-Fed Dual Active Bridge Converter … with * k p B T A K = . By choosing 45* 10 k s T T −= = , Kp = 0.276. The simulation scenario consists of 4 steps: the clamp capacitor is charged from 0 to 0.2s, at 0.2s the Vc controller starts and the LVS switches are enabled, at 0.25s the Vo controller starts and in the final step, the load changes suddenly to the nominal value. Figures 6, 7 show the simulation results of clamp and output voltage respectively. As can be observed, in the start-up period, the voltages of the two capacitors are charged and controlled to increase gradually as well as track the reference values with negligible error and no over-shoot. Fig. 5. Simulink model for the control of the CFDAB converter in boost mode. TABLE II. SIMULATION PARAMETERS Specification Symbol Value Nominal power Pn 2500W Input voltage Vin 144V Output voltage Vout 400V Duty ratio D 0.64 Clamp voltage Vc 391V Switching frequency fs 50kHz Nominal duty cycle D 0.64 Nominal phase-shifted Φ 0.241 Fig. 6. Voltage response on the clamp capacitor. Fig. 7. Voltage response on the output capacitor. Furthermore, the currents through the boost inductor and the leakage inductor with little spike in the start interval which ensure the feasibility of the control design in the experiment, are shown in Figures 8 and 9. The clamp voltage and the out voltage decrease slightly, about 3V, at 0.45s when the nominal load is changed. After that, they quickly return to the reference value within 0.01s and 0.03s. In steady-state operation, the voltages on both the LVS and HVS side of the transformer along with leakage current are shown in Figure 9. Due to the Engineering, Technology & Applied Science Research Vol. 11, No. 2, 2021, 7054-7059 7058 www.etasr.com Vu et al.: A Novel Modeling and Control Design of the Current-Fed Dual Active Bridge Converter … small difference between the reference of clamp voltage and the output voltage, the bias current in the leakage current helps HVS switches achieve the ZVS easier [16]. In addition, the switches voltage and current are presented for S1 and Q2 in Figures 10 and 11. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -10 0 10 20 30 iLdc1 iLdc2 Fig. 8. Interleaved-boost current in simulation. 0.63262 0.63263 0.63264 0.63265 -400 -200 0 200 400 Vab 0.63262 0.63263 0.63264 0.63265 -400 -200 0 200 400 Vcd 0.63262 0.63263 0.63264 0.63265 -10 0 10 iLr Fig. 9. Voltage on the two sides of the transformer and leakage current. 0.63152 0.63153 0.63154 0 200 400 0.63152 0.63153 0.63154 -10 0 10 Fig. 10. Voltage and curent on switch device S1. III. CONCLUSION The current paper presents the control structure along with the modeling of the CFDAB converter in boost mode. A small signal model is built up with the chosen modulation technique to control the output voltage of the converter. Simulations were carried out to verify both the proposed model and the control design. The simulation results prove the good performance of the control design not only in the steady-state but also in the dynamic responses. 0.637955 0.63796 0.637965 0.63797 0.637975 0 100 200 300 400 0.637955 0.63796 0.637965 0.63797 0.637975 -20 0 20 40 Fig. 11. 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