Microsoft Word - ETASR_V13_N1_pp9812-9818 Engineering, Technology & Applied Science Research Vol. 13, No. 1, 2023, 9812-9818 9812 www.etasr.com Babu et al.: Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel … Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel Hybrid Envelope Tracking Power Supply Ambily Babu ECE Department-VTU, AMC Engineering College, India ambily_babu@outlook.com (corresponding author) B. G. Shivaleelavathi ECE Department- VTU, JSS Academy of Technical Education, India shivaleelavathi1963@gmail.com Veeramma Yatnalli ECE Department- VTU, JSS Academy of Technical Education, India veeramma71@gmail.com Received: 15 October 2022 | Revised: 1 November 2022 | Accepted: 2 November 2022 ABSTRACT This paper presents the realization of an Envelope Tracking Power Supply (ETPS), for a sinusoidal envelope input signal. A parallel hybrid topology is chosen for the implementation. In this topology, a voltage-controlled Class-AB linear amplifier stage and a current-controlled switching converter stage operate in parallel. A hysteretic current control scheme is employed to control the operation of the switching converter. Block-level implementation of the ETPS is done using Simulink 2017b, continuous mode simulation. Simulations are performed using a sinewave input envelope signal = 1.94+ 1.2 sin(ω∙t). The input frequency varied from 1MHz to 60MHz. As the input frequency is increased, the ETPS moves from the linear to the non-linear region of operation. During the transition, the slew rates of the load current and the switching current match at a particular input frequency of 2MHz while the efficiency peaks. The maximum obtained efficiency while tracking the sinewave input signal is 82.3%. The way the efficiency can be optimized by focusing on the matching of the slew rates of load and switching currents is explained. Also, an insight into the study of various circuit parameters and the trade-offs that the designer needs to consider while designing an ETPS, is provided. Keywords-envelope tracking; RF power amplifiers; supply modulators; ETPS; ETPA; mobile communication; design considerations I. INTRODUCTION To cater to the ever-increasing demands of customers, RF power amplifiers in mobile communications need to deal with signals that have a very high Peak to Average Power Ratio (PAPR). Operating such an RF power amplifier with a fixed supply is no longer a viable option, as it reduces the overall efficiency as well as battery lifetime between charges. Envelope tracking is an assuring supply modulation technique [1-4] that helps improving the efficiency of such an RF power amplifier. Envelope Tracking Power Supply (ETPS) is a vital block of an Envelope Tracking Power Amplifier (ETPA), since the overall efficiency of the ETPA [5] depends on the efficiency of the ETPS as given by: �����= ����� * ����� (1) The primary goal of an ETPS designer is to develop an efficient power supply, operating at higher bandwidths. Various ETPS topologies exist [6-9], aiming to provide high efficiency while maintaining signal fidelity. A hysteretic current controlled parallel hybrid ETPS, as shown in Figure 1, is employed in this paper, as it operates efficiently at high frequencies. In this topology, a switching converter will track most of the low frequency signals, at high efficiency. The remaining high frequency signals will be tracked by the linear amplifier at a lower efficiency. The linear amplifier stage also needs to compensate for the ripples created by the switching converter, which is controlled by a hysteretic current control mechanism. The hysteretic current control mechanism offers a fast response Engineering, Technology & Applied Science Research Vol. 13, No. 1, 2023, 9812-9818 9813 www.etasr.com Babu et al.: Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel … since it employs a window comparator and hence is ideal for high bandwidth mobile applications [10-11]. Fig. 1. Hysteretic current controlled ETPS [12]. II. BLOCK LEVEL IMPLEMENTATION OF HYSTERETIC CURRENT CONTROLLED PARALLEL HYBRID ETPS A block level implementation [13] of hysteretic current controlled parallel hybrid ETPS is depicted in Figure 2. A sinusoidal signal denoted by (2) is provided as the input envelope signal: �� �= �_�� + �_�� sin(� ) (2) where �� � is the instantaneous input signal, �_�� the DC component of the input signal, �_�� sin�� � the AC component of the input signal, and �= 2π.� /� , where � /� is the input signal frequency. A Class AB amplifier with an operational trans conductance amplifier input stage is used as the linear stage, as shown in Figure 3. A single stage buck converter is used as the switching stage, as shown in Figure 4. Fig. 2. Block level implementation. Fig. 3. Linear stage. Fig. 4. Switching stage. Linear stage current, ��� is sensed by the resistor ������ and the direction of this current controls the operation of the Hysteretic Controller. The value of ������ is kept very small in order to sense the current accurately. A relay block in Simulink is used to function as a hysteretic controller. Hysteresis h is chosen to be equal to ±7mV. Initially, the linear stage starts [14-18], providing current and when the voltage drop across the ������ exceeds +7mV, the hysteretic controller will turn ON the switching converter. The switching stage starts providing the majority of the load current, as given by (3). The linear stage needs to source only the difference current during this time. � !��=��" # ��� (3) As the current provided by the switching stage increases and when the ��" exceeds the � !��, the current through ������ starts flowing in the opposite direction. When the voltage drop across ������ falls below -7mV the hysteretic controller turns the switching converter OFF. The linear stage now needs to sink current. III. REGIONS OF OPERATION OF HYSTERETIC CURRENT CONTROLLED PARALLEL HYBRID ETPS Fig. 5. Regions of operation. The working of the hysteretic current controlled [19-24] Parallel Hybrid ETPS can be explained in 3 regions, as shown Engineering, Technology & Applied Science Research Vol. 13, No. 1, 2023, 9812-9818 9814 www.etasr.com Babu et al.: Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel … in Figure 5. The circuit parameters considered for performing simulations in the 3 operating regions are mentioned in Table I. TABLE I. PARAMETERS CONSIDERED FOR SIMULATION Parameter Value Input envelope signal � =1.94+1.2 sin(2. π.� /� .t) Rsense 1Ω Rload 47Ω L 11µH h ± 7mV Vdd 5.5V A. Linear Region of Operation In this region of operation, the slew rate of switching current is greater than the slew rate of load current as represented by (4). SR i%& > SR i'()* (4) Simulations were conducted at 1MHz input frequency and the obtained results are shown in Figure 6. It can be observed that the slew rate of the switching current is greater than that of the load current. As a result, the switching frequency �� of the switching stage increases and the calculated average switching frequency of the buck converter is 6.6MHz. The linear stage current is within the hysteresis values of ±7mA. Fig. 6. ���, ��", � !�� at 1MHz � � . The load current is the sum of linear stage current and the switching stage current, as is clearly visible from Figure 6. When the inductor current ��+ is rising, the current provided by the linear amplifier decreases and vice-versa. Hence, the three currents obey (5): ��" � � # ��� (t) = � !�� (t) (5) ��" � �+ ,-.�/�0,1�/� �23.23 = 45�/� �6178 (6) Now, the switching current is: ��" � � 9 ��"_�! �� � � +��"-.:;< 2-=.76 � � 9 ��"_�! �� � � + ,-. �/� �6178 (7) Substituting the (7) in (6), we get: ! (t) - �(t) = ������ . ��"_�! �� (t) ��"_�! �� (t) = ,>�/�0,-. �/� ?@AB@A (8) This ripple current needs to be absorbed by the linear stage and, hence, the ripple voltage due to the switching current is given by: ��"_�! �� (t) . ������ = ! (t) - �(t) (9) The corresponding ripple voltage, ! (t) - � (t) obtained during the simulation is given in Figure 7. It can be observed that the ripple voltage falls within the hysteresis value of ±7mV. Fig. 7. Ripple voltage at 1MHz � � . B. Matching Slew Rate Point The slew rate of the switching current is equal to the slew rate of the load current in this operating region, as given by (10): SR i%& = SR i'()* (10) The simulation results at 2MHz input frequency are given in Figure 8. Fig. 8. ���, ��", � !�� at 2MHz � �. The average switching frequency of the converter is calculated to be 2MHz, which is equal to the input frequency. The linear stage current is slightly higher than the hysteresis values. The switching frequency is observed to be minimum at this point. The obtained corresponding ripple voltage is given in Figure 9. It can be observed that error is slightly greater than the hysteresis value of ±7mV. C. Non-Linear Region of Operation In this operating region, the slew rate of the switching current is lower than the slew rate of the load current as represented by (11): Engineering, Technology & Applied Science Research Vol. 13, No. 1, 2023, 9812-9818 9815 www.etasr.com Babu et al.: Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel … SR C�+ < SR C !�� (11) Simulations were conducted at 20MHz input frequency and the resulting current waveforms are given in Figure 10. As can be observed, the switching stage is able to provide only the DC components of the load current. The linear stage needs to provide the AC components of the load current. The average switching frequency of the converter is calculated to be 20MHz. Fig. 9. Ripple voltage at 2MHz � �. Fig. 10. ���, ��", � !�� at 20MHz � �. The error ripple voltage obtained during the simulation is given in Figure 11. It can be observed that the error has significantly increased. Fig. 11. Ripple voltage at 20MHz � �. IV. EFFICIENCY AND LOSS ANALYSIS OF ETPS The efficiency of an ETPS is given by (12): ����� = �1;<�7D� �1;<�7D�E��612232E�F612232 (12) where G!H/��I� is the average output power of the ETPS, JK !���� represents the losses occurring in the linear amplifier stage, and LM !���� the losses occuring in the switching converter stage. A. Linear Stage Losses Class AB linear stage comprises of NMOS and PMOS devices, referring to Figure 3 and the occurring total losses are the sum of the losses in NMOS and PMOS devices, as stated in (13): JK !���� = NOPL !���� + GOPL !���� (13) where: NOPL !���� = (��"- � !�� ) !H/ GOPL !���� 9 (� !�� - ��" ) ( �� - !H/ ) B. Switching Stage Losses Switching stage losses comprise of conduction losses in the diode and MOSFET, switching losses in the MOSFET, and driver losses: SK !����= MQRSTU CQR !���� + LVC UℎCRX !���� + YZC[\Z !���� (14) where: MQRSTU CQR !����= PN_SCQS\ !����+ PN_OPL !���� (15) PN_SCQS\ !���� 9 �1 ^ Y�. ��"_�� . !�_� !�� where D = !H/_�� / �� . PN_OPL !���� = D. ��"_�� _ . �!� (16) where �!� is the ON resistance of the MOSFET. LVC UℎCRX !���� = ��" . !`` .( !� + !`` ) ��+_�I� /2 where ton = Fa ,a b8c-D3c�de→g� and !`` = Fa,a b8c-D3c�ge→d� . YZC[\Z !���� = hi i� ��+_�I� (17) Linear region of operation: ��+_�I� = �23.23 � ,88 _.j D (1-D. ,2_ck2 l ,2_8m l ) Non-linear region of operation: ��+_�I� = � /� . V. ETPS SIMULATION MEASUREMENTS FOR VARYING INPUT FREQUENCY �= 1.94+ 1.2 sin(2. π.� /� t) is the input signal considered for simulation. The input frequency � /� is varied over a wide range from 1MHz to 60MHZ. Correspondingly, the average switching frequency of the switching converter, ��+ is noted down. Linear amplifier and switching converter losses are also obtained (Table II). The efficiency is calculated by (12). It can be observed that the efficiency peaks at an input frequency of 2MHz. At this frequency, SR C�+ = SR C !�� and ��+ is minimum. As a result, switching losses are minimum, as highlighted in Table II and the efficiency peaks, as shown in Engineering, Technology & Applied Science Research Vol. 13, No. 1, 2023, 9812-9818 9816 www.etasr.com Babu et al.: Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel … Figure 12. For � /� lower than 2MHz, SR C�+ > SR C !�� and hence the increased switching losses result in lowering the efficiency. For � /� higher than 2MHz, SR C�+ < SR C !�� . In this condition, the switching converter will be able to provide only the DC components of the load current. As a result, the linear amplifier needs to provide the AC components, which results in increased linear stage losses and consequently, a drop in efficiency. Hence, the efficiency of a hysteretic current controlled parallel hybrid ETPS drops as the input signal frequency increases. TABLE II. EFFICIENCY ANALYSIS FOR VARYING INPUT FREQUENCY nop (MHz) nqr (MHz) stuv (W) wxytqqzq (W) {|ytqqzq (W) } 1 6.6 0.094 0.00077 0.02151 80.8% 2 2 0.093 0.00217 0.0179 82.3% 5 5 0.094 0.03706 0.02333 60.9% 10 10 0.093 0.03915 0.02825 58.2% 20 20 0.093 0.03920 0.03821 54.6% 40 40 0.092 0.03906 0.05799 48.8% 60 60 0.093 0.03981 0.07759 44.2% Fig. 12. Input frequency versus switching frequency and efficiency. VI. DESIGN CONSIDERATIONS Various parameters like ������ , � !�� , L, h, �� need to be analyzed and considered while designing an ETPS. The main goal of an ETPS designer is to accurately reproduce the input envelope signal at maximum circuit efficiency. ������ is chosen to be very much smaller then � !�� to reduce the losses occurring in the current sense resistor. Inductor L, hysteresis h, and supply voltage �� ~ ′ are parameters determined by the designer. The simulations conducted in Section V are taken as the base to study the variations in efficiency with respect to parameter variations. The Input signal considered is: �= 1.94+ 1.2 sin(2. π.� /� t) A. Inductor, L Variations The inductor value selected for simulation in Section V was 11µH. The average slew rate of the switching current is given by (18): L� �+_�I� = _ � (1- ,-._8m ,88 ) �_�� (18) Reducing the inductor value to 5µ H increases the slew rate of the switching current. SR C�" exceeds SR C !�� and hence LK !���� increases as shown in Table III. This brings down the efficiency. Increasing the inductor value to 30µH reduces the slew rate of the switching current. SR C�" goes below SR C !�� as shown in Figure 13. As a result, the switching stage will be able to provide only the DC components of the load current and the linear stage will be forced to provide the AC components. This increases the losses occurring in the linear stage and consequently lowers the efficiency. TABLE III. EFFICIENCY ANALYSIS FOR VARYING INDUCTOR VALUES nop = 2 MHz L (µH) nqr (MHz) wxytqqzq (W) {|ytqqzq (W) }}}} 5 6.69 0.0007802 0.02147 80.1% 12 2 0.002172 0.01798296 82.3% 30 6.7 0.03757 0.02386 60.05% Fig. 13. Changes in slew rate as L changes. B. Hysteresis Variations The hysteresis value selected for the simulation was ±7mV. When it reduces to ±2mV, the switching frequency increases tremendously and hence the switching losses increase as shown in Table IV. As a result, the efficiency drops. When the hysteresis value increases to ±20mV, the switching frequency of the converter reduces drastically and the switching converter now fails to provide the entire load current. As mentioned above, this results in increased losses occurring in linear stage. Efficiency again drops. TABLE IV. EFFICIENCY ANALYSIS FOR VARYING HYSTERESIS VALUES h (mV) wxytqqzq (W) {|ytqqzq (W) }}}} 2 0.006895 0.02237 76.3% 7 0.002207 0.01798 82.3% 20 0.03045 0.02001 65.1% C. �� Variations The selected �� for simulations in Section V is 5.5V. The average slew rate of the switching current is given by (16). Simulations are performed at 1MHz input frequency and the corresponding slew rates can be observed in Figure 14. The corresponding average switching frequency obtained from simulations is 8MHz. As the �� drops to 4.5V, the L� �+_�I� drops as shown in Figure 15. The corresponding average switching frequency obtained from simulations is reduced to 6MHz. Engineering, Technology & Applied Science Research Vol. 13, No. 1, 2023, 9812-9818 9817 www.etasr.com Babu et al.: Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel … Fig. 14. L� �+ and L� !�� at �� =5.5V. Fig. 15. L� �+ and L� !�� at �� =4.5V. Fig. 16. L� �+ and L� !�� at �� =6.5V. As the �� increases to 6.5V, the L� �+_�I� increases as shown in Figure 16. The obtained corresponding average switching frequency has increased to 9MHz. Hence, by varying the supply voltage �� of the switching converter, the slew rates of the switching current can be varied to match with the slew rates of the load current and thereby to obtain maximum efficiency. VII. CONCLUSION The current paper presents a novel idea to the hysteretic current controlled parallel hybrid ETPS designers, that they should focus on matching the slew rates of switching and load currents for all frequencies of operation, in order to obtain maximum efficiency at all operating frequencies. In this paper, the hysteretic current controlled parallel hybrid ETPS is implemented in Simulink and simulations were performed using a sinusoidal envelope input signal. Efficiency analysis is performed by varying the input frequency from 1MHz to 60MHz. It was observed that the efficiency peaks for an input frequency of 2MHz, when the slew rates of the load current and the switching current matches. Ripple voltage was found to be increasing from 5.5mV to 28mV as the region of operation moved from linear to non-linear. Various circuit parameters that the designer needs to consider while designing an ETPS and its trade-offs are also discussed in length. The simulated ETPS could work for a peak efficiency of 82.3% for a switching frequency of 2MHz, while tracking the sinusoidal envelope input signal at 2MHz input frequency. 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