10646 FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 35, No 4, December 2022, pp. 619-634 https://doi.org/10.2298/FUEE2204619L © 2022 by University of Niš, Serbia | Creative Commons License: CC BY-NC-N Original scientific paper PERFORMANCE ANALYSIS AND OPTIMIZATION OF 10 NM TG N- AND P-CHANNEL SOI FINFETS FOR CIRCUIT APPLICATIONS Abdelaziz Lazzaz1, Khaled Bousbahi2, Mustapha Ghamnia1 1Laboratoire des Sciences de la Matière Condensée (LSMC), département physique, Université d’Oran 1 Ahmed Ben Bella, Oran, Algérie 2ESGEE d’Oran, Oran, Algérie Abstract. This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N- and P- channel silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been performed through simulations by using Silvaco ATLAS TCAD with the Bohm quantum potential (BQP) algorithm. The influence of the geometrical parameters on the threshold voltage VTH, the subthreshold swing (SS), the transconductance and the on/off current ratio, ION/IOFF, is investigated. The two structures have been optimized for CMOS inverter implementation. The simulation results show that the N-FinFET and the P-FinFET can reach a minimum SS value with Fin heights of 15 nm and 9 nm, respectively. In addition, low threshold voltages of 0.61 V and 0.27 V for N- and P-channel SOI FinFETs, respectively, are obtained at a Fin width of 7 nm. Key words: FinFET, CMOS, Quantum effect, Leakage current 1. INTRODUCTION Nanoelectronics is a field of engineering technology which is used for controlling device properties at the nanometric scale. To meet the increasing demands for high- performance and high-speed applications, transistors need to be aggressively scaled down. This poses huge modifications both in the development of new device structures and in the fabrication processes. When the channel length is less than 20 nm, Short-Channel Effects (SCEs) become insurmountable and, consequently, the device performance degrades. Multi-gate FETs have successfully enabled CMOS scaling and are considered to be the best alternative structures that can extend to 10 nm node technology. Received April 8, 2022; revised June 21, 2022 and June 26, 2022; accepted June 26, 2022 Corresponding author: Abdelaziz Lazzaz Laboratoire des Sciences de la Matière Condensée (LSMC), département physique, Université d’Oran 1 Ahmed Ben Bella, Oran, Algérie E-mail: lazzaz.abdelaziz@gmail.com 620 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA Most of the reported FinFETs are fabricated with a silicon channel, they present different advantages such as: i) reduced SCEs and a low leakage current, ii) superior electrostatic control through tri-gate structures, iii) reduced effect of substrate bias on the threshold voltage and excellent carrier transport properties along with more aggressive channel length scaling possibilities [1]. The conventional FinFET technology has to face the competition from other technology options because of its high access channel resistance due to its extremely thin body. To improve FinFET performance, one must address the quantum confinement problem. Hence, the use of the BQP algorithm, which is based on the Bohm interpretation of quantum mechanics [8], may become more important. N.P. Maity et al. in 2017 [22] have explored the application of the promising high-k dielectric material, HfO2, on MOS devices. They observed that the tunneling current is inversely proportional to the dielectric constant of the oxide material. Niladri Pratap Maity et al. in 2016 [23] have developed an analytical model to evaluate the impacts of the HfO2 on the current density model with a comparison between the theoretical model and the experimental measurements. Lazzaz et al. in 2022 [27] have demonstrated that quantum effects play a dominant role in nanostructures. They used the BQP method to fit experimental measurement of the IDS-VDS characteristics for 14 nm TG N-FinFET. Neha Gupta et al. in 2020 [28] have explored the performance evaluation of high-k gate stack on the analog and RF figure of merits (FOMs) of 9 nm SOI FinFET. The results of their simulation confirm that the limitations of the transistor device such as SCEs, leakage current and parasitic capacitance have been reduced and pave the way for high-speed switching and RF application due to the use of high-k dielectric material with SiO2 between gate and fin. Anisur Rahman et al. in 2018 [29] found that Intel’s 10 nm technology achieved scaling benefits over its preceding 14 nm generation at matched or better transistor reliability. Marupaka Aditya et al. in 2021 [30] have confirmed that using high-k dielectric materials increase the ON current and improve the device performance. Sanghamitra Das et al. in 2021 [31] have studied the effect of FinFET geometric parameters (channel length and fin height) on the RF FOMs by using TCAD simulations. Their results confirm that decreasing the channel length or increasing the fin height improves the RF parameters. Mostak Ahmed et al. in 2021 [31] have simulated the electrical characteristics of a 3- D TG N-channel SOI FinFET with a channel length of 5 nm using different gate dielectric materials. The results of their simulation confirm that high-k dielectric materials are the better option in the fabrication for future TG FinFET devices. The above literature survey indicates the importance of using high-k dielectrics in FinFET devices to reduce SCEs. In this paper, the transfer and the transconductance characteristics have been computed in order to find the electrical response of TG N- and P- channel SOI FinFETs with 10 nm channel length. The BQP algorithm has been used from Silvaco ATLAS TCAD software to simulate the I-V characteristics. The simulated devices have been optimized in terms of geometry to have optimal voltage transfer characteristics (VTC) for a CMOS inverter [14], [15]. Performance Analysis and Optimization of 10 nm TG N- and P-Channel SOI FinFETs for Circuit Applications 621 2. DEVICE STRUCTURE The hafnium-based oxide is extensively used because of its low leakage property and its high thermal stability with silicon [25]. The geometric parameters used in this simulation are represented in Table 1 and the operating parameters of the two structures are presented in Table 2. Table 1 Geometric parameters Symbol Designation Value L Channel length 10 nm LD, LS Drain, source length 12 nm EOT Equivalent oxide thickness 0.68 nm VDD Supply voltage (V) 0.75 V Table 2 Operating parameters Symbol Designation Value Eg Gap energy 1.12 eV k(Si) Dielectric constant of silicon 11.9 k(HfO2) Dielectric constant of hafnium dioxide 24 Nch Channel doping concentration 1016 cm-3 NS/D ΦG Source/drain doping concentration Gate work function 1021 cm-3 4.85 eV TG FinFET technology is based on the following fin geometry: fin length (L), fin width, Wfin, fin Height, Hfin, and oxide thickness, tox. The numerical resolution, which includes the gate work function and the choice of physical models, represents one of the two main steps in the Silvaco ATLAS tools. The Shockley-Read-Hall (SRH) theory has been used. Figure (1a) shows the top-view layout of TG SOI FinFET with 10 nm gate length, and Figure (1b) illustrates the 3D schematic view of FinFET. The gate oxide thickness is the same for all three sides of the fin. The Hfin is considered as the distance between the top gate and the bottom gate oxides. The Wfin is represented as the distance between front gate and back gate. LG is the gate length and BOX is buried oxide. (a) (b) Fig. 1 (a) Top-view layout of TG SOI FinFET [21], (b) 3D schematic view of TG SOI FinFET 622 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA All simulations have been performed using ATLAS and DEVEDIT 3D device simulator and different operating parameters such as the supply voltage, are extracted from the predictive technology model (PTM) [32]. 3.DRAIN CURRENT MODEL OF THE TG FINFET The device electrostatics is governed by the 3-D Poisson’s equation [5][19]: Si zyxqn dz zyxd dy zyxd dx zyxd   ),,( ² ),,(² ² ),,(² ² ),,(² =++ (1)  : Electrostatic potential; q: electron charge; εSi: silicon permittivity, n(x,y,z): electron density. Quantum effects become more dominant and are difficult to control in the device. Hence, in this study, one must consider them by selecting the appropriate model such as the BQP. The BQP model can also be used with the energy balance and hydrodynamic models, where the semi-classical potential is modified by the quantum potential in a similar way as for the continuity equations [20]. According to the Bohm interpretation of quantum mechanics, the wave function can be represented in polar coordinates by the following expression [8]: 𝜓 = 𝑅𝑒𝑥𝑝( 𝑖𝑆 ℏ ) (2) R: Probability density per unit volume; S has the dimension of an “action” (energy × time) The Schrödinger equation can be written as: )(Re)(Re)(Re 2 ² 1   iS xpE iS xpV iS xpM =+             − − (3) M-1∇S: The local velocity of the particle associated with the wave function. E is conserved and equal to the sum of the potential energy and V is the kinetic energy [8]. The quantum potential is derived from the use of the Bohm interpretation of quantum mechanics and it is described by the following equation [8][20]: R RM Q )( 2 ² 1  −= − (4) The threshold voltage expression in the case of a FinFET structure can be defined by [18]: dsdsbBSD ox b Bfbth VqN C VV    −+++= ))2(2(2 (5) Vfb: Flat band voltage; ∅B: Body potential; Cox: Gate oxide capacitance; q: electron charge; NS: Doping concentration; εs: dielectric constant of the semiconductor; Vsb: the reverse bias between the source and the body; λd: drain-induced barrier lowing (DIBL) coefficient; λds: channel length modulation; λb: barrier variation coefficient. Performance Analysis and Optimization of 10 nm TG N- and P-Channel SOI FinFETs for Circuit Applications 623 The transconductance, gm, represents the drain current variation with respect to gate voltage. It is represented by the following equation [4][13]: GS D m dV dI g = (6) SS is a major parameter for calculating the leakage current, and is calculated as [13]: )(log 10 DS GS Id dV SS = (7) The value of the DIBL is [3]: DS TH V V DIBL   = (8) VTH: threshold voltage; VDS: drain-source voltage. 4. RESULTS FinFET is considered to be a promising candidate for ultimate CMOS device structure because it has robustness against SCEs and higher current drivability. SOI FinFETs have shown several advantages over bulk FinFETs. SOI FinFET could suppress the leakage current between source and drain through the body below the channel fin, and it has low source/drain-to-substrate capacitance, thereby improving the speed characteristics. In this section, the effect of changing the fin width and the fin height is analyzed and investigated for FinFET structures. The different electrical parameters which are derived in this simulation, such as leakage and SS, are compared with other published results [9][12][17] in order to validate our model. The BQP model has better convergence properties in many situations and it can be calibrated against results from the Schrödinger-Poisson equation under conditions of negligible current flow. 4.1. Simulation and analysis SRH theory accounts for the generation and recombination of charges carriers through electron and hole capture and emission states within the energy gap. The software TCAD was used to simulate the structure and the characteristics of the TG FinFET. Figure 2 represents IDS-VGS transfer characteristics of the N-channel FinFET in linear scale with VDS = 0.7 V, which is higher than the threshold voltage. The ON current in this simulation is 4 μA when VGS = VDD. One can observe that the threshold voltage, VTH, in this simulation is 0.62 V. The VTH of the device is related to the position of the fermi level with respect to the sub-bands energy levels. Increasing the fin height will actually reduce the carrier quantum confinement, thereby reducing the sub-band energy. 624 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA Fig. 2 Transfer characteristics for N-channel FinFET To include quantum confinement in the computation of the ID-VGS characteristics, BQP has been used. As a result, a correction of the value of drain current has been achieved. Figure 3 represents the transfer characteristics in logarithmic scale. The gate voltage is swept from 0 to 0.75 V. We note that the leakage current is 10-14 A when VGS = 0 V. The leakage current obtained in this simulation is less than that obtained by Dhananjaya Tripathy et al [26]. Fig. 3 Transfer characteristics N-channel FinFET in logarithmic scale Figure 4 represents the output characteristics for N-channel SOI FinFET. We note that the drain saturation current is 2x10-6A at VDS = VDD = 0.75 V. We observe that the Early effect is more pronounced. We find that an increase in VGS will result in higher channel conductivity. The output characteristics have been obtained for VGS = 0.7 V. Performance Analysis and Optimization of 10 nm TG N- and P-Channel SOI FinFETs for Circuit Applications 625 Fig. 4 Output characteristics of N-channel FinFET Figure 5 represents the transconductance of N-channel FinFET. The gate voltage is swept from 0 to 0.75 V. We note that the maximum value of the transconductance at VDS = 0.7 V is 5x10-5 A/V. Fig. 5 Transconductance characteristics of N-channel FinFET The higher value of the transconductance can be attributed to the higher strain in the short channel device. The transconductance peak can be reduced by reducing the channel length. Shorter gate length, LG, provides less resistance and lower surface-roughness scattering, which leads to a higher transconductance and mobility. The higher mobility is induced by the quasi-ballistic transport instead of mobility increase. Table 3 represents the different performance parameters of N-channel SOI FinFET [6][11]: Table 3 Performance parameters of N-channel FinFET Parameter Value ION 4 µA IOFF 10-14 A ION/IOFF 4x108 VTH 0.62 V DIBL 21.05 mV/V SS 79.48 mV/dec 626 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA The values of SS and DIBL indicate a performance comparable with the state of the art obtained in PTM 10 nm HP NMOS and PMOS, such as the value of SS which is 102.4 mV/dec and DIBL which is 212 mV/V. But, we must optimize these values in order to have a good performance of the device [17]. The SS provides a good performance comparable to the one obtained by Ajay Kumar et al [12], and the calculated performance ratio is better than that obtained by Buryk et al [9]. Figure 6 represents the transfer characteristics of P-channel FinFET in linear scale with VSD = 0.7 V. We note that the ON current in this structure is 6.25x10 -5 A. The ON current is measured at VSG = VDD= 0.75 V. The value of the threshold voltage in this simulation is 0.30 V. The performance ratio, ION/IOFF, calculated in this simulation is higher than that calculated by A.S. Opanasyuk et al [9]. Fig. 6 Transfer characteristics of P-channel FinFET Figure 7 represents the transfer characteristics of P-channel FinFET in logarithmic scale. We note that the leakage current is 1.58x10-8 A when VSG = 0 V. Fig. 7 Transfer characteristics in logarithmic scale of P-channel FinFET Performance Analysis and Optimization of 10 nm TG N- and P-Channel SOI FinFETs for Circuit Applications 627 Figure 8 represents the output characteristic of P-channel FinFET. We note that the drain current saturation is 5.5x10-5 A. Fig. 8 Output characteristics P-channel FinFET Table 4 represents the different performance parameters: Table 4 Performance parameters of P-channel FinFET Parameters Values ION 5.5x10-5 A IOFF ION/IOFF VTH SS 2.51x10-8 A 2.19x103 0.31 V 133.50 mV/dec 4.2. Effect of the fin height In this section, we investigate the impact of the fin height variation on ID-VGS characteristics. Quantum effects are included in the simulation. We think that the calculated optimized values of heights in N- and P-channel FinFETs can be used as geometric parameters in the PTM for the design of CMOS inverters. Fig. 9 Transfer characteristics with different fin heights for N-channel FinFETs 628 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA Figure 9 represents the transfer characteristics of N-channel FinFETs with different height values, 9 nm, 11 nm, 13 nm and 15 nm. It is clear that as we increase the fin height, the ON current increases from 2.5 μA up to 4 μA. The ON current allows the driving capability of the device. The increase of fin height increases the inversion charge density and thereby increases the ON current [24]. We note that the leakage current increases with the increase of the fin height because trap-assisted-tunneling is more important than direct tunneling. Table 5 represents the impact of fin height on the subthreshold swing and the threshold voltage of the simulated device: Table 5 Impact of fin height of N-channel FinFET Parameter 9 nm 11nm 13nm 15nm SS (mV/dec) 73.86 78.57 79.76 83.75 VTH (V) 0.67 0.66 0.65 0.64 We note that the increase of fin height increases the subthreshold swing, and the threshold voltage decreases in the device. The increase of the subthreshold swing is due to the increase in the total capacitance, so we need to minimize the parasitic capacitance in order to reduce the power consumption. The decrease of the threshold voltage VTH is due to the decrease of the fermi level. Figure 10 represents the impact of fin height on the performance ratio (ION/IOFF). We note that the increase of fin height up to 13 nm decreases the performance of the device. The performance ratio increases because of the decrease of leakage current [2]. Fig. 10 The impact of fin height on the performance ratio of N-channel FinFET The suitable value of fin height for the simulated device is 15 nm because it shows a larger performance ratio equal to 4x109. Figure 11 represents the impact of fin height variation on P-channel FinFET transfer characteristics. We note that the ON current increases with the increase of fin height. We note that the leakage current increases with increase of fin height because direct tunneling is more important than trap-assisted-tunneling. Performance Analysis and Optimization of 10 nm TG N- and P-Channel SOI FinFETs for Circuit Applications 629 Fig. 11 Impact of Fin height on the transfer characteristics of TG P-channel FinFET Table 6 displays the impact of fin height on subthreshold swing and VTH in 10 nm P- channel FinFET. Table 6 Impact of Fin height on P-channel FinFET Parameter 9 nm 11 nm 13 nm 15 nm SS (mV/dec) 129.62 137.50 133.33 133.50 VTH (V) 0.35 0.33 0.32 0.31 The variation of subthreshold swing is due to the total capacitance of the device. The threshold voltage in P-channel FinFET decreases with increasing fin height. Figure 12 illustrates the impact of fin height on performance ratio of P-channel FinFET. We note that the increase of fin height until Hfin = 13 nm decreases the performance ratio, then the performance ratio increases when Hfin > 13 nm because of the decrease of the leakage current[2]. Fig. 12 Impact of fin height on the performance ratio of P-channel FinFET The suitable value of this optimization is 9 nm because it allows a desirable performance ratio. 630 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA 4.3. Effect of Fin width In this section, we investigate the impact of fin width on the performance of N-channel FinFET. Fig. 13 Impact fin width on N-channel FinFET Figure 13 shows the transfer characteristics of N-channel FinFET for different values of fin width. The gate voltage is swept from 0 V to 0.75 V. We note that the ON current increases from 4x10-6 A up to 5.25x10-6 A, then it falls down to 3.30x10-6 A because the strain effect in the channel increases. The large fin width decreases the mobility and the inversion charge and results in a smaller drain current. The leakage current increases from 10-14 A up to 3.16x10-12 A when fin width is 9 nm. When fin width is greater than 9 nm, the leakage current decreases down to 1.58x10-13 A because direct tunneling is more important than the trap-assisted-tunneling. The following Table 7 represents different values of subthreshold swing and VTH for different fin widths. We note that the subthreshold swing and the threshold voltage increase with increasing fin width. Because of the quantum effects along the WFin direction, the channel electrons will populate the discrete sub-bands. The VTH will increase because more gate-bias is required to populate electrons into the lowest sub band, which is significantly above the bottom of the conduction band by eVTH. It should be underlined that a large fin width allows the enlarging of the total gate width therefore, the gate and depletion capacitance increases and subthreshold swing increases [16]. Table 7 Impact of Fin width of N-channel FinFET Parameter 7 nm 8 nm 9 nm 10nm SS (mV/dec) 95.31 106.89 114.54 171.05 VTH (V) 0.61 0.62 0.63 0.65 Figure 14 illustrates the performance ratio of N-channel FinFET, we note that ION/IOFF decreases down to 1.66x106 with Wfin = 9 nm then, the performance ratio increases up to 4x108.The increase of the performance ratio is due to the decrease of leakage current [2]. Performance Analysis and Optimization of 10 nm TG N- and P-Channel SOI FinFETs for Circuit Applications 631 Fig. 14 Impact of width fin on the performance N-channel FinFET Transistor dimensions are scaled down in order to improve drive current and circuit speed and the ratio ION/IOFF is needed to exceed 10 6 [2]. The suitable value of fin width on N-channel FinFET is 10 nm because it has the best performance ratio 4x108. Fig. 15 Impact of fin width on P-channel FinFET Figure 15 represents the impact of fin width on the transfer characteristics of P-channel FinFET, we note that the ON current increases and the maximum value is 6.25x10-6 A. The increase of fin width increases the leakage current in the device after Wfin=9 nm because direct tunneling current is more important than trap-assisted-tunneling. Figure 16 represents the impact of fin width on performance ratio of P-channel FinFET. We notice that the performance of device decreases with increasing fin width up to 9 nm, then above this value, it starts to increase [2]. 632 A. LAZZAZ, K. BOUSBAHI, M. GHAMNIA Fig. 16 Impact of fin width on the performance ratio of P-channel FinFET Table 8 represents the different results of subthreshold swing and VTH of P-channel FinFET: Table 8 Impact of Fin width of P-channel FinFET. Parameter 7 nm 8 nm 9 nm 10nm SS (mV/dec) 168.75 175.01 132.01 137.25 VTH (V) 0.27 0.28 0.33 0.35 The increase of threshold voltage is due to the presence of the sub bands. The quantum confinement raises the conduction band edge, EC, to the lower order eigenvalues. This shift has a direct influence on the device threshold voltage because as it requires more band bending (potential energy lowering) in order to create the inversion layer [10]. The variation of subthreshold swing is due to the total capacitance of the device [7]. The suitable value of fin width in P-channel FinFET is 7 nm because it has a larger performance ratio of 4x102. 5. DISCUSSION AND CONCLUSION Throughout this study, we have shown that both N- and P-channel FinFETs have good performance ratios only when short-channel effects are minimized. We have also shown that the BQP algorithm is a good simulation tool for computing parameters that control the quantum effects. It also allows the calculation of the optimal geometrical parameters for optimal performance of devices that can be implemented in CMOS circuits. The results show that in order to have a good threshold voltage, one needs to increase the fin height that allows the increase of the energy level of the sub-bands. To minimize the SCEs, the subthreshold swing must be around 60 mV/dec and the total capacitance must be decreased in both devices by using high-k oxides and wide thicknesses. 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