Instruction FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 30, N o 3, September 2017, pp. 375 - 382 DOI: 10.2298/FUEE1703375D MIXED MODE PERFORMANCE OF GAAS UTB-MOSFET WITH EXTRA INSULATOR REGION AND UNDOPED BURIED OXIDE REGION  Shiva Prasad Das 1 , Ananya Dastidar 2 , Partha Sarkar 1 , Sushanta K. Mohapatra 3 1 Department of Electronics and Communication Engineering, Centre for Advanced Post Graduate Studies, Biju Patnaik University of Technology, Odisha, India 2 Department of Instrumentation and Electronics, College of Engineering and Technology, Bhubaneswar, BPUT, Odisha, India 3 School of Electronics Engineering, KIIT University, Bhubaneswar, Odisha, India Abstract. Investigation of mixed mode performances for GaAs UTB-MOSFET at nanoscale regime keeping in view of “Beyond CMOS” is the current trend of semiconductor industry. Here it is proposed to modify conventional models by considering an extra Insulator Region (IR) and Undoped Buried oxide Region (UBR) to study the performance related to digital and analog/RF applications. Here a GaAs is considered as the channel material. The IR- UTB-SOI-n-MOSFET has shown promising results with respect to SS, DIBL, fT and switching speed. Key words: Silicon-On-Insulator, UTB MOSFET, GaAs, DIBL, Analog/RF Performance, Insulator Region. 1. INTRODUCTION In recent years, there has been a growing demand of Integrated Circuits (ICs) providing better analog/ RF applications as well as digital functionalities [1]–[3]. The Silicon-On- Insulator (SOI) technology [1], [4], [5] based Fully Depleted (FD) Silicon On Insulator MOSFETs are widely used for mixed mode application ICs as it offers sharp sub-threshold slope, high current drive, high transconductance, reduced parasitic capacitance, and absence of latch-up which are key parameters for digital applications [6]–[8]. Due to high transconductance to drain current (gm/Id) ratio and low body factor, the FD-SOI-MOSFETs have been used to design low power circuits to operate at a high and low frequency as Received September 17, 2016; received in revised form November 30, 2016 Corresponding author: Sushanta K. Mohapatra School of Electronics Engineering, KIIT University, Bhubaneswar, Odisha, India (E-mail: skmctc74@gmail.com) 376 S. P. DAS, A. DASTIDAR, P. SARKAR, S. K. MOHAPATRA well as high temperature providing better performance than the conventional MOSFETs [9], [10]. The use of high electron mobility material like GaAs is promising as it has higher saturated electron velocity, higher electron mobility, allowing it to function at much higher frequencies, less noise and be operated at higher power levels than Silicon [11], [12]. Previously it has been shown by Orouji et al. [13] that SOI-MOSFETs with an extra Insulator Region (IR-SOI) in which the silicon active layer and drain region consists of an insulator region (HfO2) provides high electron reliability due to low gate leakage current and low critical electric field. The Self Heating Effect (SHE) which is one of the drawbacks of FD-SOI has been reduced by a new structure Undoped Buried Region MOSFET (UBR- MOSFET) [14]. In this paper, the analog/ RF performance along with some scaling parameters of Ultra Thin Body (UTB) SOI n-channel MOSFET (UTB-SOI-n-MOSFET) has been examined along with UTB-SOI-MOSFET with extra Insulator Region (IR-UTB-SOI-n-MOSFET), UTB-n-MOSFET with Undoped Buried Region under channel (UBR-UTB-SOI-n-MOSFET) and a new structure UTB-SOI-n-MOSFET with extra insulator region and undoped buried region under channel (IR-UBR-UTB-SOI-n-MOSFET) with the help of the device simulator from SILVACO TCAD[15]. 2. DEVICE STRUCTURE AND SIMULATION SETUP The schematic representation of four different structures UTB-SOI-n-MOSFET, IR- UTB-SOI-n-MOSFET, UBR-UTB-SOI-n-MOSFET and IR-UBR-UTB-SOI-n-MOSFET, which was considered for the 2-D simulation is given in Fig.1. The Effective Oxide Thickness (EOT), the gate length (LG), the GaAs body thickness (tGaAs), the SiO2 Buried Oxide Thickness (tBOX) and Si Substrate thickness (tSUB) have been taken of 1.1 nm, 60 nm, 10 nm, 50 nm and 100 nm respectively in all the four type of structures. The source extension (LS) and the drain extension (LS) have been taken as 70 nm each. The source and drain area are highly doped with n-type donor ions with concentration 10 20 /cm 3 each to reduce the mobility degradation due to coulombs scattering. The silicon substrate is diffused with p-type acceptor ions with concentration 10 18 /cm 3 and the GaAs channel region is doped with p-type acceptor ions with concentration 10 16 /cm 3 to avoid threshold voltage variation[16]. The metal gate work function is set to 4.6 eV during simulation[17]. The structures are calibrated to meet the requirement of International Technology Roadmap for Semiconductors (ITRS) in 45 nm technology node [18]. The 2-D numerical device simulator [15] ATLAS is used for the simulation of the proposed structures. The drain bias is fixed to VDD =1.0 V as per ITRS [19]. To study the Analog/ RF performance the simulation is carried out at the drain to source voltage VDS = 0.5 V (half of the supply voltage i.e. VDD/2) [20] with a variable gate to source voltage (VGS) 0 V to 1.0 V. The threshold voltage is obtained by using constant current ID =10 -6 A/µm, from ID~VGS characteristic curve. In the channel region the electron and hole Shockley-Read-Hall [21],[22] generation and recombination lifetime, τn and τp are set to the value 1×10 -8 sec each. In material models, Lombardi mobility model [23] is used which considers the effect of transverse electric fields along with doping and temperature dependent parameters GaAs UTB-MOSFET with Extra Insulator Region 377 of mobility [24]. The numerical solution used here is based on the drift-diffusion approach [25]. Some other material models have also been used here like the concentration dependent (CONMOB), parallel electric field dependence (FLDMOB) which is required for measuring velocity saturation effect, Shockley-Read-Hall (SRH) and optical [15]. The Fermi-Dirac model helps to get the result close to ideal values by a Rational Chebyshev approximation [19]. (a) (b) tGaAs tBOX tSUB LC LS LD SOURCE GATE DRAIN SUBSTRATE LC UBR (c) (d) Fig. 1 Schematic Device structures (a) UTB-SOI-n-MOSFET (b) IR-UTB-SOI-n-MOSFET (c) UBR-UTB-SOI-n-MOSFET (d) IR-UBR-SOI-n-MOSFET Table 1 Structure notation Notation used in this article Structure A UTB-SOI-n-MOSFET B IR-UTB-SOI-n-MOSFET C UBR-UTB-SOI-n-MOSFET D IR-UBR-UTB-SOI-n-MOSFET 378 S. P. DAS, A. DASTIDAR, P. SARKAR, S. K. MOHAPATRA 3. RESULT ANALYSIS As described previously these four types of structures were simulated using 2-D numerical device simulator and the parameters like the on-state drive current (ION), off-state leakage current (IOFF), ION/IOFF ratio, threshold voltage (Vth) and power dissipation variation were evaluated which are some of the factors affecting the scaling properties of the devices. The surface potential variation with respect to channel length was also observed. The RF/ Analog performance analysis was done by measuring the parameters like transconductance (gm), total capacitance (CTotal), Q-factor and cut-off frequencies (fT) for the four different structures. A Sub-threshold Slope (SS) was calculated by using the following equation [19]. ( / ) (log ) GS D V SS mV dec I    (1) Another vital parameter responsible for scaling effect is the Drain Induced Barrier Lowering (DIBL) which was also evaluated by the following equation[26]. (a) (b) Fig. 2 Surface Potential Variation along channel for A, B, C and D at VGS = 1 V (a) at VDS = 0.05 V (b) at VDS = 1 V (a) (b) Fig. 3 ION and IOFF comparison for A, B, C and D (a) at VDS = 0.05 V (b) at VDS = 1 V GaAs UTB-MOSFET with Extra Insulator Region 379 1 2 0.95 th thV V DIBL   (2) Where Vth1 and Vth2 are threshold voltages at VDS = 0.05 V and VDS = 1 V. Fig.2 shows the surface potential variation along the channel of the structures A, B, C and D, where Fig. 2 (a) shows the variation of surface potential along the channel for the four structures at drain to source voltage VDS = 0.05 V and Fig. 2 (b) shows the surface potential variation along the channel for the four structures when VDS = 1 V. The trade-off between IOFF and ION has been shown in the Fig. 3 for different structures. Fig. 3(a) shows the ION and IOFF comparison between A, B, C and D at VDS = 0.05 V and Fig. 3(b) shows the ION and IOFF comparison between A, B, C and D at VDS = 1 V. At VDS = 0.05 V structure C gives better ION/IOFF ratio and at VDS = 1 V, structure B shows significant improvement in ION/IOFF ratio. (a) (b) Fig. 4 (a) Static Power Dissipation for A, B, C, and D, (b) Threshold Voltage Variation at VDS = 0.05 V and VDS =1 V In the Fig. 4(a), the static power dissipation (PD = IOFF x VDD) [27] variation with respect to the four type of structures is presented. The structure B provides lower static power dissipation than the other three structures. The Fig. 4(b) provides the threshold voltage variation of the four structures at VDS = 0.05 and VDS = 1 V. The extracted value of threshold voltage, sub-threshold slope, DIBL and static power dissipation are tabulated for all device structures in table 2. In Fig. 5, the trans-conductance i.e. D m GS I g V    (3) for different A, B, C and D has been given. The Fig. 5(a) and Fig. 5(b) show the gm variation with ID for the given four structures at VDS = 0.05 V and VDS = 1 V respectively. 380 S. P. DAS, A. DASTIDAR, P. SARKAR, S. K. MOHAPATRA (a) (b) Fig. 5 Trans-conductance (gm) variation with ID for A, B, C and D (a) at VDS = 0.05 V (b) at VDS =1 V (a) (b) Fig. 6 (a) Total Capacitance (CTotal) with ID for A, B, C and D at VDS =1 V (b) a Cut-off Frequency (fT) variation with ID for A, B, C and D at VDS =1 V In Fig. 6(a), the variation of total capacitance (CTotal = Cgd + Cgs ) for A, B, C and D has been given at VDS = 1 V where Cgd is parasitic gate to drain capacitance and Cgs is the parasitic gate to source capacitance. Another important parameter, a cutoff frequency (fT) has been plotted in Fig. 6(b) 2 ( ) m T gs gd g f C C   (4) The Q-Factor (gm/SS) has been calculated for the four device structures and given in the Table 3. GaAs UTB-MOSFET with Extra Insulator Region 381 Table 2 Performance parameters-1 Structure Vth1 (V) Vth2 (V) SS1 (mV/dec) SS2 (mV/dec) DIBL (mV/V) PD (x10 -12 W) A 0.420 0.403 69.81 71.95 17.678 1.92 B 0.420 0.404 69.68 71.83 17.589 1.82 C 0.505 0.436 74.11 82.21 72.923 6.55 D 0.505 0.437 74.01 81.90 71.872 6.04 Table 3 Performance parameters-2 Structure ION1/IOFF1 (x10 -9 ) ION2/IOFF2 (x10 -8 ) CTotal (fF/µm) fT (x10 -11 Hz) Q-Factor A 1.686 3.920 1.639 2.00 24.21 B 0.681 4.132 1.655 2.03 9.32 C 2.095 1.034 1.629 2.00 23.07 D 0.773 1.120 1.639 2.03 7.68 4. CONCLUSIONS A comparative performance analysis of a new structure was presented namely a IR- UBR-UTB-SOI-n-MOSFET which contains an extra Insulator Region (IR) at the channel source junction, Undoped Buried Region and having a GaAs under the channel region. The scaling and RF parameters of IR-UBR-UTB-SOI-n-MOSFET have been obtained along with conventional UTB-SOI-n-MOSFET. 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