Instruction FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 30, N o 2, June 2017, pp. 161 - 178 DOI: 10.2298/FUEE1702161P SPICE MODELING OF IONIZING RADIATION EFFECTS IN CMOS DEVICES  Tatjana Pešić-Brđanin Faculty of Electrical Engineering, University of Banja Luka, Republic of Srpska, Bosnia and Herzegovina Abstract. Electric characteristics of devices in advanced CMOS technologies change over the time because of the impact of the ionizing radiation effects. Device aging is caused by cumulative contribution of generation of defects in the gate oxide and/or at the interface silicon-oxide. The concentration of these defects is time and bias-dependent values. Existing models include these effects through constant shift of voltage threshold. A method for including ionizing radiation effects in Spice models of MOS transistor and FinFET, based on an auxiliary diode circuit using for derivation of values of surface potential, that also calculates the correction time-dependent voltage due to concentration of trapped charges, is shown in this paper. Key words: Ionizing radiation effects, Trapped charges, Spice model, CMOS devices 1. INTRODUCTION With aggressive scaling of device dimensions in CMOS technologies, which includes the decrease of oxide thickness and the increase of doping concentration in the channel, the susceptibility of the most CMOS technologies has been reduced. Scaling of the oxide thickness caused the decrease of concentration of fixed charge in the oxide, because the value of the concentration is directly proportional to the oxide thickness. On the other side, the increase of doping concentration in the channel decreased the oxide trapped charge effect on the surface potential of the channel, which also caused robustness of the components on ionizing radiation [1]. However, recent studies showed that the negative bias temperature instability damage and hot carrier injection damage were attributed to the charges trapped in the oxide (with areal density Nox) and/or at the interface of the silicon and oxide layers (with energy density distribution Dit) [2-4]. Therefore, trapped charges still represent a potential radiation threat and have measurable impact on the integrated circuits performances [2,5].  Received November 2, 2016 Corresponding author: Tatjana Pešić-Brđanin Faculty of Electrical Engineering, Patre 5, 78000 Banja Luka Republic of Srpska, Bosnia and Herzegovina (E-mail: tatjanapb@etfbl.net) 162 T. PEŠIĆ-BRĐANIN A harmful effect of ionizing radiation on CMOS devices can be diminished by using well-known techniques, such as radiation-hardening-by-process (RHBP) and radiation- hardening-by-design (RHBD) techniques [6,7]. However, even with significant efforts in RHBP and RHBD techniques, the capability of estimating the influence of ionizing radiation on electric characteristics of devices in advanced technologies are still improper [8]. Analysing of test IC circuits on ionizing radiation is quite expensive [7], so the incorporation of ionizing radiation effects in devices compact models used in standard electric circuits simulators is put upon as an alternative. The incorporation of these effects needs the knowledge of physical processes which contribute to emerging of the defects due to ionizing radiation and the impacts which these effects have on the electric characteristics of components in advanced CMOS technologies [8,9]. Numerous existing techniques for modelling these effects in circuit simulators are based on the fixed change of threshold voltage (threshold voltage shift), not considering the special impact which these defects have on the electric characteristics of the transistors [2,10-12]. Previously derived surface-potential based non-quasi static MOS model (NQS MOS model) and non-quasi static SOI model (NQS SOI model) can be modified as to include these effects of oxide trapped charges and interface trapped charges is described in this paper [13,14]. 2. IONIZING RADIATION EFFECTS IN CMOS DEVICES The main cause of the damage that occurs in CMOS devices after ionizing radiation is the generation of the electron-hole pairs in the oxide (or another dielectric) as a material that is the most sensitive to ionizing radiation in CMOS devices. After the generation of the electron-hole pairs, some of the pairs are immediately recombined. Since the electron mobility in the oxide is considerably bigger that the hole mobility [15,9], the electrons will be soon swept out of the oxide or the dielectrics, while the holes will move slowly through the oxide to the interface SiO2-Si, causing long-term effects of the ionizing radiation. Fig. 1 shows the processes after the ionizing radiation. Fig. 1 Processes in the oxide after the ionizing radiation [16] Spice Modeling of Ionizing Radiation Effects in CMOS Devices 163 Vacancies in the oxide or the dielectrics can trap the generic holes. A total amount of trapped charge in the oxide is Nox. The trapped charge changes the threshold voltage thV of CMOS devices for the threshold voltage shift [17]: , 2 ox oxox th Ntq V   (1) where q is the electron charge, tox is the oxide thickness and ox is the oxide permittivity. The threshold voltage shift Vth is negative, which means that in the case of the NMOS transistor the off current increases, while in the case of the PMOS transistor the total value of threshold voltage Vth increases, as shown in Fig. 2(a). It can be concluded from (1) that Vth depends on the square of the oxide thickness; with the decrease of the oxide thickness in nanometer CMOS technologies and due to the change of the threshold voltage the oxide trapped charge will be smaller. Fig. 2 Illustration of the threshold voltage shift Vth due to the oxide trapped charges (a) and increase in subthershold swing due to interface trapped charges (b) [17] After the ionizing radiation, the generation of interface traps occurs, which concentration is Nit. The generation holes react with hydrogen atoms in the oxide, making in such a way H + ions [18]. These ions move by drifting to SiO2-Si interface, and create 164 T. PEŠIĆ-BRĐANIN dangling bonds (i.e. Pb centres) [2]. Interface trapped charges are often linked with the permanent effects of components aging [2,10]. Fig. 2(b) shows the impact of the generation of trapped charges at the SiO2-Si interface on the transfer characteristic of the transistors. It can be noted that these charges increase the swing in the device subthreshold region. For NMOS and PMOS transistors, the generation of interface trapped charges decreases the transistor off current. 3. NQS MOS AND NQS SOI TRANSISTOR MODELS Static and dynamical characteristics of transistors can be described by set of basic equations, which are comprised of Poason's equation, drift-diffusion and continuity equations [19]. Since MOS transistor modelling is three dimensional problem, solving these sets of equations is complex and memory demanding. However, for numerous practical applications of MOS transistors, changes in the third direction can be neglected and problem can be reduced to two dimensional problem (to x and y direction). 3.1. NQS MOS transistor model In [13] a physically based NQS MOS transistor model is described, which belongs to a group of models based on surface potential. Fig. 3 shows equivalent model scheme, which as a subcircuit can be embedded into electric circuit simulators. External elements of transistor model (resistors and capacitors) can be modelled in a similar way as in other stationary or non-stationary models. Unlike some known models [20-22], in the NQS MOS model there are no analytical expressions for node currents, but they are obtained after the solution of equivalent circuit shown on Fig. 3(a). This subcircuit has two parts, as shown on Fig. 3(b):  Internal part is connected to transistor gate terminal. This part of the model is, in fact, equivalent line that models drift-diffusion transport of electrons in transistor channel;  External part is connected to source, drain and gate terminals, and it contains current-controlled current sources iS1 and iSN. This part of the circuit is defined by the potential of source, drain and substrate that is obtained by mirroring the currents which flow through voltage sources S1 and SN. Voltage generators S1 and SN copy values of boundary surface potentials to subcircuit in the source end and the drain end of channel. Voltage generator VB serves to copy bulk polarisation to equivalent subcircuit. Capacitance Coxk represents gate-oxide capacitance (Coxk = Cox / N). The other model elements Rk and Ck, non-linear channel resistance and depletion region capacitance, are respectively defined by the equations: 3 31/ 1 2 1 4 5 6 (1 ( )) (1 ( ( )) ) , ( ) A A GS Sk Sk Sk k GB fb Sk Sk A V A R A A V V A                (2) 1/ 20 7 ( ) , 2 bk Si ch k Sk Sk Sk Q qN C A           (3) Spice Modeling of Ionizing Radiation Effects in CMOS Devices 165 where the constants A1  A7 are physically based, Nch is doping concentration in the channel and Si is the silicon permittivity. Surface potential of every cell is denoted with Sk. The derivations for (2) and (3) and the expressions for A1  A7 are given in [13]. (a) (b) Fig. 3 NQS MOS model (a) and the equivalent subcircuit (b) In a surface charge-sheet model, which describes MOS transistor operation [23], the boundary channel potentials S1 and SN at the source and drain side are functions of biasing voltage of transistor terminals through the following recurrent relations [24]: 166 T. PEŠIĆ-BRĐANIN 2 1 1 12 1 1 2 ln ( ) , S f SB T GB fb S S T V V V V V                    (4) 2 2 1 1 2 ln ( ) . SN f SB DS T GB fb SN SN T V V V V V V                     (5) In the previous equations  is the body factor, VT is the thermal voltage, f is the channel potential (=VT ln(Nch/ni))) and Vfb is the flatband voltage. Since the equations (4) and (5) are implicit relations, to determine surface potentials S1 and SN there are several iterative methods proposed in the literature [25]. In the NQS MOS model, relations (4) and (5) are determined by diode circuits. For any point y in the channel is: 2 2 1 1 exp( / ) 1 exp(2 / ) ( ) 1. Sy T fy T GB fb Sy Sy T V V V V V                     (6) By comparing the equation (6) with the diode current expression: 0 (exp( / ) 1) d Sy T ss I I V I   (7) the conclusion is that: 2 2 0 1 1 exp(2 / ) ( ) 1, 1. ss fy T GB fb Sy Sy T I V V V V I                    (8) When determining the boundary surface source potential S1, in the equation (8) Sy and fy should be replaced with Sy = S1 and fy = 2f + VSB, consecutively, while for determining boundary surface potential on the drain side SN instead Sy and fy should be used SN and 2f + VSB + VDS, respectively. Owning to this type of analysis, it is possible to construct a circuit for solving equations (7) and (8), which is comprised of a diode (with unit current I0 = 1) and voltage-controlled current source, where the current is calculated by the equation (8). Figure 4 shows this type of auxiliary diode circuit. For determining both boundary surface potentials, 1S and SN , there are used two identical diode subcircuits and the described method is used to solve the equations (4) and (5). The values of the boundary surface potentials determined in this way are copied with voltage generators S1 and SN (shown in Fig. 3(b)) on the input and output of equivalent circuit to solve the transport of the electrons in the channel. Knowing the boundary surface potentials allows us to calculate the values of nonlinear resistors and capacitors Rk and Ck, namely to determine the transistor currents. Fig. 4 Diode subcircuit for solving surface potentials Spice Modeling of Ionizing Radiation Effects in CMOS Devices 167 A physical base of the NQS MOS model in an easy way allows including significant effects shown in aggressive scaling of transistor dimensions, like, for example, short channel effects and quantum-mechanics effects. 3.2. NQS SOI transistor model A compact model for n-channel fully depleted SOI MOS transistor with double gate (FD SOI transistor) is developed based on the NQS MOS model, and it is applicable for asymmetrical and symmetrical planar structures [14]. In non-stationary model of FD SOI MOS transistor (NQ SOI model), a transistor is represented by parallel connection of two SOI transistors with one gate, as shown in Fig. 5, to model current in a front and back channel [14]. Fig. 5 Schematic presentation of FD SOI transistor (a) and its electric equivalent (b) By comparison with the NQS MOS model, recurrent expressions for calculating boundary surface potentials in the NQ SOI model also contains the influence of biasing of both gates. So the boundary surface potentials in channel S1 and SN in the FD SOI transistor are connected with biasing of front (VGF) and back (VGB) gate, and biasing between drain and source VDS with new recurrent relations [26,27]: 1 11 1 2 2 2 1 12 2 2 / / // / 1 1 1 ( ) ( ) ( ) ( ) ,f T S T S TB T B T oxF GF fbF S GF fbB B oxB V V VV V T T S B t V V V V t V e e e V e e                             (9) 2 2 2 2 2 ( 2 ) / / / / / 1 ( ) ( ) ( ) ( ) ,f DS T Sn T Bn T Sn T Bn T oxF GF fbF Sn GF fbB Bn oxB V V V V V V T T Sn Bn t V V V V t V e e e V e e                               (10) where, in the case of fully depleted silicon layer, boundary potentials of back channel can be expressed as: ,and 22 11 Si Sich SnBn Si Sich SB tNqtNq      (11) while for a fully symmetrical transistor applies toxF = toxB. In the equations (9)-(11) the index F relates to the front gate, and the index B relates to the back gate. Recurrent 168 T. PEŠIĆ-BRĐANIN relations (9) and (10) are calculated with the assumption that the difference of Fermi’s potentials between the source and the drain is equal to the voltage VDS. Electric potential distribution in the channel through depth, i.e. in the line of axis x, is obtained by solving these recurrent relations (Fig. 6). Fig. 6 Electric potential distribution in the channel through depth of FD SOI transistor For applications in the NQ SOI model for a symmetrical FD SOI MOS transistor, recurrent equations for calculating boundary surface potentials can be written with basic algebraic transformations [14] in the following form: / / 1 2 ( ) ( ) ,Sx T Sx T V V S S S I e I e I     (12) while: 2 2 2 2 2 1 1 ( ) ,ch Si ch Si S GF fbF Sx GF fbB Sx T Si Si qN t qN t I V V V V V                           (13) ,exp1 2 / 1                   SiT SichTVfx S V tNq eI   (14) ,exp1 2 2          SiT Sich S V tNq I  (15) where on the source side Sx = S1 and fx = 2f , while on the drain side the changes have to be made Sx = Sn and fx = 2f + VDS. In the previous expressions, tSi is the silicon film (body) thickness. Auxiliary diode circuits, similar to the NQS MOS model for solving recurrent relations, are used in this way for calculating boundary values of surface potentials in the NQ SOI model. Fig. 7 shows equivalent diode circuit for solving the equation (12) [14]. Fig. 7 Diode subcircuit for solving surface potentials in NQS SOI model Spice Modeling of Ionizing Radiation Effects in CMOS Devices 169 4. INCLUSION OF NOX AND DIT IN NQS MOS AND NQS SOI MODELS A physical foundation of previously described models allows easily inclusion of effects important for transistor operation. Modelling of the effects of generation interface trapped charge with energy density distribution Dit and oxide trapped charge with areal density Nox is possible in NQS MOS and NQS SOI model by changing the surface potential equations. It is possible to model the impact of these effects onward on the characteristics of transistor in two ways: 1. Auxiliary diode circuits, with the included effects of Nox and Dit, are used for determining surface potentials for use in NQS MOS and NQS SOI models or 2. Auxiliary diode circuits, with the included effects of Nox and Dit, are used for determining surface potentials, and then to connect consecutively to gate of some standard models (for example, BSIM 4 for MOS transistor or BSIM.CMG for FinFET). A total amount of electric charge caught in oxide is: ,oxox qNQ  (16) while a total amount of interface charge [19]: , 2 2/           f g it gE FE ititit E E qDdEDqQ (17) where Eg / 2 is the midgap energy level at the interface and Ef is the energy of Fermi level. If we add and subtract the factor Egb / 2, where Egb is the bulk midgap energy level, to the factors in the equation parenthesis (17) we have:  . 222 222 fSit f gbggb it gb f gbg itit qD E EEE qD E E EE qDQ                                      (18) As stated in the Section 2, charges Qox and Qit have impact on the change of the transistor voltage threshold. This change can be expressed by correction potential nt [6]: [ ( )]. ox it nt ox it S f ox ox Q Q q N D C C         (19) In the NQS MOS model, the equations (4)-(6) are modified in a way to include correction potential nt. Eqn. (6) in a modified form with included correction potential is: 2 2 1 1 exp( / ) 1 exp(2 / ) ( ) 1. Sy T fy T GB fb Sy nt Sy nt T V V V V V                         (20) 170 T. PEŠIĆ-BRĐANIN For determining surface potential Sy, two identical diode circuits are used, as shown in Fig. 3(b). In the NQS SOI model, for a symmetrical FD DG SOI transistor, the equation for surface potential is modified in a way to include nt in the following way: 1 11 1 2 2 1 12 ( 2 ) / / // / 1 1 1 ( ) ( ) ( ) ( ) .f DS T S T S TB T B T GF fbF nt S GF fbB nt B bV V V VV V T T S B V V V V V e e e V e e                               (21) The parameter b, which appears in the equation (21), can have the value b = 0 for the source end of the channel and b = 1 for the drain end of the channel (in accordance with the equations (9) and (10)). However, the main problem in modelling of trapped charges with (21) is the fact that the distribution of surface potential in the channel depends not only on gate voltage, but also on drain voltage VDS due to split of quasi Fermi levels [19]. It means that the concentration Qit will change along the channel, even for the constant Nit. The impact of the changeable charge Qit along the channel can be modelled with a modified value of the parameter b  (0,1). In the equation (21) it is calculated with in advance known value, and it is possible with the fine tuning [28] to accomplish better match of the model results with the results of 2D TCAD numeric simulator Silvaco Atlas [29]. The equation (21) can also be solved with auxiliary diode circuits (Fig. 7) with: 2 2 2 2 2 1 1 ( ) ,ch Si ch Si S GF fbF nt Sx GF fbB nt Sx T Si Si qN t qN t I V V V V V                               (22) ,exp1 2 /)2( 1                   SiT SichVbV S V tNq eI TDSfx   (23) .exp1 2 2          SiT Sich S V tNq I  (24) The surface potential S from the diode circuit in Fig. 7 represents the equation solution (21) for any combination of voltage variables VDS and VGS. 5. SIMULATION RESULTS AND DISCUSSION The ionizing radiation has the effects on the changes of the electric characteristics of the transistor. In the paper, the approaches described in the Section 3 are used for the simulation of electric characteristics of the transistor and the results are compared with numerical results. Spice Modeling of Ionizing Radiation Effects in CMOS Devices 171 5.1. Modeling of Nox and Dit effects in MOS transistor Including of the effects Nox and Dit in the NQS MOS transistor model is made by incorporation of the correctional potential nt in the surface potential equation (eqn. 20). As already stated, with diode circuits as in Fig. 4, by using mathematical apparatus available in the Spice, the boundary surface potentials are acquired, and based on them the equivalent line is solved (Fig. 3). In this paper, the equivalent line is divided on 10 equal segments. Fig. 8 shows the acquired surface potentials that show the impact of Nox (Fig. 8(a)) and the impact of the interface trapped charges through Dit on the surface potential value. The results acquired with diode circuits are shown with solid line, while the numerical results are shown with open circles. A solid compliance of the results confirms the efficiency of the diode circuit as a new method for solving iterative relations (21). As it can be seen on the figure, the surface potential is changed for constant negative voltage shift with the increase of Nox, while Dit = 0. In the case of the increase of Dit while Nox = 0, the voltage shift of the surface potential will depend on its value due to the dynamic charge contribution on SiO2-Si interface. Namely, the interface charges have the energy inside forbidden zone. Interface trapped charges with energies above intrinsic energy level Ei behave as acceptor-like charges, while all interface trapped charges with energies below intrinsic energy level behave as donor-like charges, which is experimentally verified [2,30,31]. Fig. 8 Surface potential versus gate voltage dependence for different values of Nox at Dit = 0 (a) and for different values of Dit at Nox = 0 (b) obtained from Spice simalation of proposed model (solid line) and TCAD numerical results (open circles) for MOS transistor with tox = 5 nm and Nch = 410 17 cm 3 Fig. 9 shows the transfer characteristics of MOS obtained from the Spice and compared with TCAD numerical results, which shows solid compliance of the results of the applied method in NQS MOS model with the TCAD numerical results. It is important to state that in [2] is used the same expression for correctional potential due to the effects of ionizing radiation, by using voltage-controlled voltage source (VCVS) with voltage: )(),,,( SitoxSBGBDF fDNVVfV  (25) 172 T. PEŠIĆ-BRĐANIN and which is series connected to transistor gate, for which some of standard models are used (for example, BSIM model). For determining VDF = nT, respectively solving (19) the authors used the non-iterative algorithm inside the Verilog-A model [2], while in our method the iterative equation for determining the surface potential was solved in a physical way, with diode subcircuits. Fig. 9 Transfer characteristics ID(VGS) for different values of Nox at Dit = 0 (a) and for different values of Dit at Nox = 0 (b) obtained from Spice simalation of proposed model (solid line) and TCAD numerical results (open circles) 5.2. Modeling of Nox and Dit effects in FinFET With the scaling of the device dimensions, conventional transistors reached its limits, so new technological structures for future generations of integrated circuits are emerging. Such structure is fully-depleted floating-body (fin) multi-gate FET (FinFET) [32]. However, recently it has been shown that FinFET technology has rapid rate of aging, so that the degradation on FinFET exceeds the degradation of the planar technology node by higher stress voltage and longer time [33]. Therefore, the modelling of ionizing radiation effects in these structures is important. In the standard BSIM.CMG model [34] for FinFET, however, there is only fitting parameter CIT (interface trap capacitance parameter) in sub-threshold region [35], while it does not have a possibility for user-defined input of oxide trapped charges. Fig. 10 shows a schematic presentation of n-type FinFET analysed in this paper (with the following parameters L = 0.9 m, tox = 5 nm, tSi = 20 nm, Nch = 2.410 18 cm 3 and ND = 10 20 cm 3 ). Fig. 10 Schematic representation of n-type FinFET Spice Modeling of Ionizing Radiation Effects in CMOS Devices 173 Fig. 11 shows the output characteristics of transistor obtained by using TCAD numerical results, BSIM.CMG model which parameters are acquired by fitting, and modified NQS SOI model. In order to simplify the tuning of the parameters of BSIM.CMG model, a simulate structure has a long channel and the thickness of oxide gate and silicon fin, so the effects of a short channel can be neglected, and the silicon fin is fully depleted [28,36]. The same parameter set is used for p-type FinFET, with the fact that the fin film has the opposite doping (n-type fin film). In the absence of the ionizing radiation effects, the compliance of results of different models is shown [28]. Fig. 11 The output characteristics of n and p-type FinFETs simulated for Nox = 0 and Dit = 0 with Spice using BSIM.CMG model (solid line), NQS SOI model (dashed line) and TCAD simulator Silvaco Atlas (open circles) Modeling of Nox and Dit effects by using auxiliary diode subcircuits (ADS) for solving surface potential equations (21) is possible in two ways: by using NQS SOI model (time consuming), or as shown in [2,6], for determining surface potential as control voltage of VCVS for producing VDF = nt = f (VGB, VSB, Nox, Dit). This VCVS is connected in series with gate node of BSIM.CMG model, as shown in Fig. 12. Second approach of modelling the ionizing radiation effects in FinFET is at time more comfortable, because the simulation execution time is shorter and there are no problems due to convergence, but due to a physical dependency the NQS SOI model is more convenient, because other effects important for the operation of FINFET can be easily included (for example, quantum-mechanic effects). The second approach, BSIM.CMG model with ADS, was used in this paper for modelling the ionizing radiation effects. 174 T. PEŠIĆ-BRĐANIN Fig. 12 Schematic of diode subcircuit shown together with the BSIM.CMG FinFET model as implemented in Spice simulations to include the effects of Nox and Dit Fig. 13 shows transfer characteristics of n and p-type FinFETs for different values of Dit while Nox = 0. Fig. 14 shows transfer characteristics for different values of Nox while Dit = 0, and Fig. 15 shows characteristics for combinations of different values of Nox and Dit. In Figs. 14 and 15 there are no results obtained by BSIM.CMG model because oxide trapped charge effect is not included in this model. All characteristics are generated for VDS = 1.2V. In the BSIM.CMG model, a parameter CIT is determined for given Dit. Parameter b, which appears in the equation (21), was used with value b = 0.05, for the reason previously explained in Section 4. All stated characteristics show good match of suggested approaches with TCAD numerical results [28,37]. Fig. 13 Transfer characteristics ID(VGS) for different values of Dit at Nox = 0 Spice Modeling of Ionizing Radiation Effects in CMOS Devices 175 Fig. 14 Transfer characteristics ID(VGS) for different values of Nox at Dit = 0 Fig. 15 Transfer characteristics ID(VGS) for combined influence of Nox and Dit for n-type FinFET Fig. 16 shows changes of threshold voltages for n and p-type FinFETs after ionizing radiation, obtained from TCAD and proposed method. The constant current method is used for threshold voltage extraction [28,38], with I'D = 100 nA/m. The impact of this ionizing radiation effect is also experimentally confirmed [39]. 176 T. PEŠIĆ-BRĐANIN Fig. 16 Theshold voltages Vth for p and n-type FinFET as function of Nox and Dit. 6. CONCLUSION The modelling of ionizing radiation effects for CMOS devices is presented in this paper. It is shown how surface potential equations can be modified with correctional potential, which is a result of existence of oxide charges and interface trapped charges. Auxiliary diode circuits were used for determining modified surface potentials, while for obtaining electric characteristics of devices, two approaches were used, previously developed non-stationary models for CMOS devices and, second approach, VCVS (with controlled voltage obtained by diode circuits) in series with gate node of standard models. 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