Instruction FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 31, N o 2, June 2018, pp. 257 - 265 https://doi.org/10.2298/FUEE1802257V IMPACT OF CHANNEL ENGINEERING (SI1-0.25GE0.25) TECHNIQUE ON GM (TRANSCONDUCTANCE) AND ITS HIGHER ORDER DERIVATIVES OF 3D CONVENTIONAL AND WAVY JUNCTIONLESS FINFETS (JLT)  B. Vandana 1 , Jitendra Kumar Das 1 , Sushanta K. Mohapatra 1 , Suman Lata Tripathi 2 1 School of Electronics Engineering, KIIT University, Bhubaneswar, Odisha, India 2 Electronics and communication Engineering, Lovely Professional University, Jalandhar, Punjab, India Abstract. The paper explores the analog analysis and higher order derivatives of drain current (ID) at gate source voltage (VGS), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium (Si1-0.25Ge0.25) device layer. In view of this, the performances are carried out for different gate length (LG) values (15-30 nm) and current characteristics determined by maintaining constant ON current (ION 10 -5 ) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high ID induces as the LG scales down. With respect to this the constant ION determine ID, transconductance (gm), transconductance generation factor (TGF) and its higher order terms (g \ m, and g \\ m) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (ND = 1.7x10 19 cm -3 ) and metal workfunction (ϕM = 4.6 eV) are responsible to achieving reduced SCEs. Key words: SiGe JL FinFET, channel engineering, molefraction, analog parameters, higher order derivatives, short channel parameters (SC). Received May 25, 2017; received in revised form October 23, 2017 Corresponding author: B. Vandana School of Electronics Engineering, KIIT University, Bhubaneswar, Odisha, India (E-mail: vandana.rao20@gmail.com) 258 B. VANDANA, J. K. DAS, S. K. MOHAPATRA, S. L. TRIPATHI 1. INTRODUCTION Due to the tremendous growth in technology, the exploration of novel architectures has become mandatory for ultra large scale integration (ULSI) applications. Among various architectures, the FinFET has become an attractive device solution for down scaling the SCEs. As the device dimensions have moved to nanometer range [1]–[4], this primarily owes to its superior gate control over channel. Multi-gate structures like Silicon on insulator (SOI) MOSFETS [5], [6] are scaled down to decananometer range, however realizing these MOSFETS in decananometer [7] range requires extremely sharp source/drain p-n regions which are possibly achieved through high end annealing techniques and there by increases the fabrication cost. To overcome these difficulties a new MOSFET without source/drain p-n junction was proposed [8], [9], and named junctionless nanowire transistor. The comparative study was performed between fabricated Junctionless FinFET (JLT) and conventional bulk FinFET, realizing the SCEs as discussed in [10]. Heavily doped JLT induces fully depleted channel in the subthreshold region with high vertical electric field (E- field). The E-field is neutral at the inversion mode of operation and the shift in VTH occurs when the bands (ϕM – ϕS) are flat at flat band voltage (VFB) [9]. The absence of doping concentration gradients eliminates diffusion impurities and the sharp doping profile problem. The paper explores the multi-gate JL FinFET topology which is an extended work of [11], [12], this mainly concentrating the analog performances and the higher order gm parameters using ID characteristics. The probabilistic analyses of higher order derivatives are also important to study at scaled LG, the major issues that emphasize the analog and higher order derivatives are important for advance communication system. Non-linearity characteristics realizes unwanted disturbances with frequencies differences at input once, which generates Intermodulation Distortion (IMD) at output stage [13]–[15]. The higher order analysis and the inter-modulation harmonics are important to maintain minimal linearity’s at the RF stage [16]. Accordingly, at pre-fabrication process the analog performance parameters are necessary at nanoscale regime. The paper discusses the higher order derivative parameters of 3D conventional and Wavy JL FinFETs using channel engineering scheme. Along with the introduction, Section 2 discusses the device architecture specifications and the simulation procedure undertaken, Section 3 includes the comparative analysis on analog performances of these devices using Si1- 0.25Ge0.25 material as device layer. Finally, the conclusion is drawn. 2. DEVICE DESCRIPTION AND SIMULATION FRAMEWORK The multi-gate transistors are the basic step to scale down the SCEs, the challenges and the issues are discussed in [17] and their performance metrics is given in [18]. A thin dual gate approach on SOI with the volume inversion is reported in [5], [19]. The another representation using 2D planar UTB and 3D non-planar approach is first given by [20], [21] later provides the detailed analysis with several performance metrics analyzed and reported in [22]–[24]. The significance of the FinFET provides better layout area efficiency in the digital circuits [25]. In general, the Fin utilizes the availability of single Fin per pitch, in which most of the pitch area is unused. To overcome this, the FinFET limits the current per pitch technology representation. Therefore, the pitch area in FinFET utilizes fully Channel Engineering (Si1-0.25Ge0.25) technique on gm (Transconductance) and its Higher Order Derivatives 259 depleted SOI (FD-SOI) topology which is grown epitaxial and merged with the 2D- FinFET forming a single device with common gate [21]. Utilizing these two approaches, a comparative analog analysis has been performed using channel engineering technique (SiGe material) with the Junctionless FinFET topology. In this section the architectural representation of conventional JL devices and Wavy-JLT is shown in Fig. 1(a), (b). Accordingly, the parameters required to construct the devices are tabulated in Table 1. The structural design is observed for different LG for 15-30 nm with a uniform doping concentration ND = 1.7 x10 19 cm -3 , and using high-k (HfO2) gate side wall spacer’s. The simulations are carried out using sentaurus TCAD [26] simulator. Phillips Unified Mobility Model is used with Lombardi model to account for high-κ induced carrier mobility degradation as considered [27]. For a deeper understanding of the quantum confinement effect, the thickness of Fin and UTB determine the density gradient based quantization models that are used. Inversion Accumulation layer Mobility model includes doping and transverse field dependency, which in turn accounts for a Coulomb impurity scattering being used. (a) (b) (c) Fig. 1 A 3D representation of (a) Conventional JL FinFET, (b) Wavy-JL FinFET at LG = 15-30 nm (c) ID-VGS characteristics of Conventional and Wavy JL FinFET at LG = 20 nm and x = 0.25. To account for the longitudinal and vertical electron field an effective intrinsic density, OldSlotboom band gap narrowing model [28], Shockley-Read-Hall mechanism for generation and recombination [29], and quantum mechanical effects are included. The device physical properties are discretized onto a non-uniform mesh of nodes and simulated with appropriate parameterization models [30]. The same models are considered for the 260 B. VANDANA, J. K. DAS, S. K. MOHAPATRA, S. L. TRIPATHI simulation study to observe the performance of the devices. With respective to this, the ID-VGS characteristics are plotted and shown in Fig. 1(c) and the ION ranges constant for both the device, but a small improvement in ID is observe for 3D Wavy-JLT. Table 1 Parameter required for simulation. Parameters 3D JL FinFET 3D Wavy-JL FinFET SiGe device layer (WFin) 7 nm 7 nm SiGe device layer (HFin) 30 nm 30 nm Silicon thickness (TSi) --------- 10 nm Donor doping (ND) 1.7x10 19 cm -3 1.7x10 19 cm -3 EOT of gate dielectric (TOX) 1 nm 1 nm Gate work Function (ϕM) 4.6 eV 4.6 eV Drain Supply Voltage (VDD) 0.05 V, 0.7 V 0.05 V, 0.7 V Channel length (LG) 15-30 nm 15-30 nm Underlap S/D (LUS, LUD) 5 nm 5 nm Molefraction (x) 0.25 0.25 Total Device Length (LT) 110 nm 110 nm Total Device Width (LW) 32 nm 32 nm (a) (b) (c) (d) Fig. 2 Transfer characteristics of (a) JL FinFET and (b) Wavy-JL FinFET for varying LG = 15-30 nm at ND = 1.7 x10 19 cm -3 , ϕM = 4.6 eV. As shown in Fig. 2a and 2b, the ID-VGS is plotted in logarithmic and linear scales, an improvement in ION and IOFF is observed for Wavy-JL FinFET. The device layer (S/D and channel) is Si1-xGex material with molefraction x = 0.25. Considering x = 0.25, Channel Engineering (Si1-0.25Ge0.25) technique on gm (Transconductance) and its Higher Order Derivatives 261 substituting this value of x, results in high content of Si in SiGe material. Therefore, the device acquires the properties of Si material, and accordingly the simulation data are extracted. The conduction mechanism of JLT seems to be similar to that of IM devices, JL device with no concentration gradients across the S/D channel regions and high N– type doping profile induces a volume inversion mechanism. From the Fig. 2 it is analyzed that, as the LG is scaled down, the ION enhances and IOFF reduces, on this point of view the performance of the device is identified using SiGe channel. In Fig. 2C and 2D the ID is plotted along the VGS for the different value of x at LG = 20 nm, from this it is realized that as the value of x increases the shift in VTH takes place which there reduces the IOFF. 3. RESULTS AND DISCUSSIONS The section deals with the results and discussions carried out for the simulation study. The higher order gm of ID characteristics results in the second and third order (g \ m, g \\ m) parameters. Further, these parameters result in second and third order intermodulation and linearity performances. In MOS circuits, harmonic distortion occurs due to the nonlinearity exhibited by higher-order derivatives of ID-VGS characteristics. Therefore, the circuits realize balanced topologies, due to this the even-order harmonics are cancelled out. The third order harmonic, which represents g \\ m, determines a lower limit of distortion and hence amplitude should be minimized. Thus, reducing g \\ m and increasing the gm acts as a sustainable solution to improve device linearity[31]. (a) (b) Fig. 3 TGF and gm as a function VGS (a) JL FinFET and (b) Wavy-JL FinFET for different LG = 15-30 nm at ND = 1.7 x10 19 cm -3 , ϕM = 4.6 eV and x = 0.25. The Fig. 3 represents TGF (gm/ID) and gm the values are extracted from the measured values of ID and plotted as a function of VGS as illustrated in Fig. 2(a, b). The graphs exhibit different dimensions of LG, JL transistors, and show that a lower gm is induced at room temperature because of the reduced carrier mobility with that of the IM devices. The mobility is an important parameter for evaluating gm, but the other factors may also affect this parameter. According to the drift equation the current that flows through the device layer has a great impact on the mobility, E-Field, and ND. This can be identified without including the mobility degradation models to the simulator and measured at different dimensions. The parameter TGF is observed as the available gain per unit value of power dissipation. From the Fig. 3 gm increases as the ID increases for scaled LG, but 262 B. VANDANA, J. K. DAS, S. K. MOHAPATRA, S. L. TRIPATHI the TGF decreases as the LG scales down. However, the TGF values are near to the ideal values and but the gm values are very high for JL FinFET. (a) (b) Fig. 4 g \ m as a function VGS (a) JL FinFET and (b) Wavy-JL FinFET for different LG = 15-30 nm at ND = 1.7 x10 19 cm -3 , ϕM = 4.6 eV and x = 0.25. (a) (b) Fig. 5 g \\ m as a function VGS (a) JL FinFET and (b) Wavy-JL FinFET for different LG = 15-30 nm at ND = 1.7 x10 19 cm -3 , ϕM = 4.6 eV and x = 0.25. Table 2 SC parameters 3D JL FinFET at VDS = 0.7V. LG (nm) S-Ssub (mV/decade) ION x10 -5 (A/μm) IOFF x10 -10 (A/μm) 15 70.446 2.70 0.190 20 80.12 2.30 2.57 25 81.419 2.28 2.01 30 70.905 2.37 0.20 Table 3 SC parameters for Wavy-JL FinFET at VDS = 0.7V. LG (nm) S-Ssub (mV/decade) ION x10 -5 (A/μm) IOFF x10 -11 (A/μm) 15 66.702 2.99 2.24 20 66.545 2.83 2.12 25 66.427 2.69 2.02 30 66.357 2.55 1.94 Channel Engineering (Si1-0.25Ge0.25) technique on gm (Transconductance) and its Higher Order Derivatives 263 Table 4 SC parameters at different values of X for JL FinFET VDS = 0.7V, LG = 20 nm. X S-Ssub (mV/decade) ION x10 -5 (A/μm) IOFF (A/μm) 0.25 80.12 2.30 2.57x10 -10 0.5 78.662 2.05 7.48x10 -11 0.75 77.449 1.42 1.79x10 -12 Table 5 SC parameters at different values of X for 3D Wavy-JL FinFET VDS = 0.7V, LG = 20 nm. X S-Ssub (mV/decade) ION x10 -5 (A/μm) IOFF (A/μm) 0.25 66.545 2.83 2.12 x10 -11 0.5 66.89 2.48 7.44 x10 -12 0.75 67.319 1.47 9.88 x10 -14 The higher order derivatives of ID (g \ m and g \\ m) as a function VGS for different LG at VDS = 0.7 V are plotted in Fig. 4 and 5 respectively. Usually for better linearity properties there should be a lesser distortion amplitude of g \ m and g \\ m. The value of VGS at which the higher order of transconductance parameters (g \ m and g \\ m) becomes zero is known as zero crossover point (ZCP) which decides the optimum bias point for device operation [15], [32]. Therefore, from the Fig. 4 and Fig. 5 the minimal higher order derivative shows better for Wavy-JL FinFET. The comparison of SC parameters for JLT devices at LG variation is tabulated in Tables 2 and 3, and at fixed LG with different values of x is given in Table 4 and 5. From the overall simulation study the Wavy- JLT explores good improvement in ION and possess less sensitivity to SCEs over the conventional one. 4. CONCLUSION The paper investigates the performance study of analog analysis and higher order parameters for both conventional and Wavy JLFinFET for different LG variations. Due to the equal amount of doping profiles along the device layer the ION is improved and IOFF is decreased. The conduction mechanism of JL FinFET with the concept of SiGe device layer is explained at different values of x. The simulation results are extracted at VDSAT values at x = 0.25, ϕM = 4.6 eV are considered to estimate the ID characteristics and the higher order parameters are evaluated accordingly. From the results it has been observed that the higher order parameters show minimal non-linearity distortions performance for Wavy-JL FinFETs over conventional JLT. Therefore, the performance of the 3D Wavy- JL FinFET shows better channel controllability through gate and thereby enhances the ID. On the other hand, the high ND with the effective channel length and width of the depletion layer are also responsible to achieve scaled SCEs. 264 B. VANDANA, J. K. DAS, S. K. MOHAPATRA, S. L. TRIPATHI REFERENCES [1] C. Hu, “Finfet and other new transistor technologies. Univ. of California. article. Finfet and other new transistor technologies,” 2011. [2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, and others, “Sub 50-nm finfet: Pmos,” in Technical Digest. International of the Electron Devices Meeting, IEDM’99., 1999, pp. 67–70. [3] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, 2000. [4] S.-Y. Kim and J. H. Lee, “Hot carrier-induced degradation in bulk FinFETs,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 566–568, 2005. [5] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi, and K. Murase, “Ultimately thin double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 830– 838, 2003. [6] J. P. Colinge, “The new generation of SOI MOSFETs,” Rom. J. Inf. Sci. Technol, vol. 11, no. 1, pp. 3– 15, 2008. [7] T. Rudenko, S. Barraud, Y. M. Georgiev, V. Lysenko, and A. Nazarov, “Electrical Characterization and Parameter Extraction of Junctionless Nanowire Transistors.,” J. Nano Res., vol. 39, 2016. [8] J.-P. Colinge, C. W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, and others, “SOI gated resistor: CMOS without junctions,” in Proceedings of the IEEE International SOI Conference, 2009, pp. 1–2. [9] A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” in Proceedings of the ESSDERC Conference, 2010, pp. 357–360. [10] R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-Orabi, and K. Kuhn, “Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm,” IEEE Electron Device Lett., vol. 32, no. 9, pp. 1170–1172, 2011. [11] B. Vandana, B. S. Patro, S. K. Mohapatra, and J. K. Das, “Exploration towards Electrostatic Integrity for SiGe on Insulator (SG-OI) on Junctionless Channel transistor (JLCT),” Facta Universitatis, Series: Electronics and Energetics, vol. 30, no. 3, pp. 383-390, 2017. [12] B. Vandana, B. S. Patro, J. K. Das, and S. K. Mohapatra, “Physical insight of junctionless transistor with simulation study of Strained channel,” ECTI Trans. Electr. Eng. Electron. Commun., vol. 15, no. 1, pp. 1–7, 2017. [13] P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, “An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design,” IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3263–3268, 2012. [14] Y. Pratap, S. Haldar, R. S. Gupta, and M. Gupta, “Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design,” IEEE Trans. Device Mater. Reliab., vol. 14, no. 1, pp. 418–425, 2014. [15] S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Linearity and analog performance analysis in GSDG- MOSFET with gate and channel engineering,” in Proceedings of the Annual IEEE India Conference (INDICON), 2014, pp. 1–5. [16] B. Razavi and R. Behzad, RF microelectronics, vol. 2. Prentice Hall New Jersey, 1998. [17] J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222–2229, 2002. [18] S. K. Mohapatra, “Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications,” 2015. [19] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. 8, no. 9, pp. 410–412, 1987. [20] L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, S. Bagchi, C. Parker, J. Vasek, and D. Sing, “Inverted T channel FET (ITFET)-Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.,” in Technical Digest IEEE International Electron Devices Meeting, IEDM ., 2005, pp. 713–716. Channel Engineering (Si1-0.25Ge0.25) technique on gm (Transconductance) and its Higher Order Derivatives 265 [21] W. Zhang, J. G. Fossum, and L. Mathew, “The ITFET: A novel FinFET-based hybrid device,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2335–2343, 2006. [22] A. N. Hanna, M. T. Ghoneim, R. R. Bahabry, A. M. Hussain, and M. M. Hussain, “Zinc oxide integrated area efficient high output low power wavy channel thin film transistor,” Appl. Phys. Lett., vol. 103, no. 22, p. 224101, 2013. [23] A. N. Hanna, A. M. Hussain, and M. M. Hussain, “Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits,” in Proceedings of the 73rd Annual Device Research Conference (DRC), 2015, pp. 201–202. [24] K. P. Pradhan, P. K. Sahu, and R. Ranjan, “Investigation on asymmetric dual-k spacer (ADS) Trigate Wavy FinFET: A novel device,” in Proceedings of the 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 137–140. [25] J.-W. Yang and J. G. Fossum, “On the feasibility of nanoscale triple-gate CMOS transistors,” IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159–1164, 2005. [26] http://www.synopsys.com/, “Sentaurus TCAD User’s Manual,” in Synopsys Sentaurus Device, Synopsys, 2012. [27] D. B. M. Klaassen, “A unified mobility model for device simulation-I. Model equations and concentration dependence,” Solid. State. Electron., vol. 35, no. 7, pp. 953–959, 1992. [28] J. Del Alamo, S. Swirhun, and R. M. Swanson, “Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon,” in Proceedigns of the 1985 International Electron Devices Meeting, 1985, vol. 31, pp. 290–293. [29] W. Shockley and W. T. Read Jr, “Statistics of the recombinations of holes and electrons,” Phys. Rev., vol. 87, no. 5, p. 835, 1952. [30] S. Saha, “MOSFET test structures for two-dimensional device simulation,” Solid. State. Electron., vol. 38, no. 1, pp. 69–73, 1995. [31] N. Aggarwal, I. Gupta, K. Sikka, and R. Chaujar, “TCAD Linearity Performance Evaluation of Gate Workfunction Engineering in Surrounding Gate Silicon Nanowire MOSFET,” Nanoscale, vol. 9, no. B, p. 10, 2012. [32] S. Kang, B. Choi, and B. Kim, “Linearity analysis of CMOS for RF application,” IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 972–977, 2003.