Instruction FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 27, N o 4, December 2014, pp. 613 - 619 DOI: 10.2298/FUEE1404613M RESOLVING THE BIAS POINT FOR WIDE RANGE OF TEMPERATURE APPLICATIONS IN HIGH-K/METAL GATE NANOSCALE DG-MOSFET  Sushanta K. Mohapatra, Kumar P. Pradhan, Prasanna K. Sahu Nanoelectronics Lab., Department of Electrical Engineering, National Institute of Technology, Rourkela, Odisha India Abstract. This article investigates the Zero-Temperature-Coefficient (ZTC) bias point and its associated performance metrics of a High-k Metal Gate (HKMG) DG-MOSFET in nanoscale. The ZTC bias point is defined as the point at which the device parameters are independent of temperature. The discussion includes sub threshold slope (SS), drain induced barrier lowering (DIBL), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd) and intrinsic gain (AV). From the results, it is confirmed that there are two different ZTC bias points, one for IDS (ZTCIDS) and the other for gm (ZTCgm). The points are obtained as: ZTCIDS=0.552 V and ZTCgm =0.410 V, which will open important opportunities in analog circuit design for wide range of temperature applications. Key words: DG-MOSFETs, HKMG, SCEs, Analog FOMs, ZTC point. 1. INTRODUCTION The growing interest and demand in designing circuits that operate at high temperatures which will be used in the military, automobile, nuclear, and some industries need to be analysed in nanoscale. Silicon on Insulator (SOI) based CMOS devices have the potential for the operation at both low and high temperatures. It is desirable to bias the digital and analog circuits designed for high temperature applications at a point where the V-I characteristics show little or no variation with respect to temperature. This point is typically known as ZTC point [1-5]. Previously, Shoucair [1] and Prijic, et al. [3] have identified the ZTC point for a bulk CMOS in both linear and saturation regions for temperatures between 25 0 C - 200 0 C. Researchers like Groeseneken, et al. [4] and Jeon, et al. [5] have shown the existence of the ZTC point for SOI MOSFET’s. Osman, et al. [6] presented a systematic analysis of ZTC point for partially depleted (PD) SOI MOSFET over a wide range of temperatures (25 0 C - 300 0 C), and identified two distinct ZTC points, in the linear as well as in the saturation region. Tan, et al. [2] identified that the ZTCIDS Received July 3, 2014; received in revised form September 14, 2014 Corresponding author: Sushanta K. Mohapatra Nanoelectronics Lab., Dept. of Electrical Engineering, National Institute of Technology, Rourkela, 769008, Odisha India (e-mail: skmctc74@gmail.com) 614 S. K. MOHAPATRA, K. P. PRADHAN, P. K. SAHU exists in both linear and saturation regions, whereas the ZTCgm lies only in the saturation region for fully depleted (FD), lightly doped, enhanced mode SOI n-MOSFET. The Double Gate (DG) MOSFET fabricated on SOI wafers is one of the most promising candidates due to its attractive features of low leakage currents, high current drivability (Ion) & transconductance (gm), reduced short channel effects (SCEs), steeper subthreshold slopes, and suppression of latch-up phenomenon [7-10], and also it is a very good option for analog applications [11-14]. Hardly any work has been reported to investigate the ZTC point for multi-gate technology. The behaviour of ID is exactly opposite after a certain VGS with variation in temperatures. This is due to the degradation in mobility or high electric field effect at higher gate bias [2]. As far as we know, this is a unique attempt to investigate the detailed analysis of ZTC point over a wide range of temperatures (100 K-400 K) for analog applications of a DG MOSFET with HKMG technology. Various performance metrics of the device have been systematically examined, which includes the SCEs like SS, DIBL, Ion/Ioff ratio, and some important analog figures of merit (FOMs) such as gm, gd, Av. 2. DEVICE DESCRIPTION AND SIMULATION SETUP In the 2-D numerical simulation, a symmetric device structure as shown in Fig. 1(a) has been modelled. The silicon channel is covered above and below by oxide layers as gate stack (GS) of equivalent oxide thickness (EOT) having 1.1 nm. Metal gate work function is considered as 4.6 eV. The channel length is 40 nm with a fixed width of 1 μm has been considered. Source and drain extensions are 60 nm with contacts vertically placed (S and D, respectively). The doping profile for channel (p-type 110 16 cm −3 ) and source, drain (n-type 110 20 cm −3 ) are set. (a) (b) Fig. 1 (a) Schematic structure of Nanoscale HKMG Double Gate N-MOSFET (b) Calibration between simulation and experimental data of Threshold voltage as a function of temperature. The 2-D numerical device simulator ATLAS is employed to simulate the planner DG- MOSFET with high-k/metal gate technology. According to ITRS the drain bias has been fixed at VDD = 1.0 V [15]. To study the analog performance the simulation is performed with Analysis of ZTC Point in HKMG-DG-MOSFET for Analog Application 615 VDS = 0.5 V and VGS = 0 V to 1.0 V. In the simulation, the inversion-layer Lombardi constant voltage and temperature (CVT) mobility model has been used, that takes into account the effect of transverse fields along with doping and temperature dependent parameters of the mobility. The Shockley–Read–Hall (SRH) generation and Auger recombination model are used for minority carrier recombination. The model Fermi-Dirac uses a Rational Chebyshev approximation that gives results close to the exact values. The model Temperature is used for various operating temperature in Kelvin which is varied from 100 K to 400 K. The interface trapped charges during the pre and post fabrications process are a common phenomenon, and these charges cannot be neglected in nanoscale device fabrication. Presence of trapped charges creates an additional non-linear potential and varying electric field across the gate dielectric. According to (1), the high-k gate stack reduces the electric field across the layer of gate stack due to high permittivity. So a lower electric field will require inducing inversion layer charge as [16]. ch di iQ   (1) Where Qch is inversion charge, di permittivity of dielectric and Ei is electric field. Even if, the fixed oxide and interface trapped charge densities are very large, it requires moderate potential across the high-k gate stack layer. Consequently, the reduction of threshold voltage and supply voltages can be maintained at reasonable values. This low electric field promotes gate stack reliability with huge unwanted charges inside. As the device is high-k gate stack, the interface trapped charge effects are included in the simulation. The trapped charge densities are considered at semiconductor to insulator interface. The typical concentration of trapped charges considered in this work is 410 11 cm -2 at interface [17]. The electron and hole surface recombination velocity is considered as 110 4 cm/sec. In the simulation all the junctions of the structure are assumed to be abrupt in nature. Furthermore, we have chosen two numerical techniques, Gummel and Newton, to obtain solutions [17]. Fig. 1(b) shows excellent agreement with the nature of threshold voltage between our simulation results and experimental data for a wide range of temperature reported in [4]. 3. RESULTS AND DISCUSSION In this section, the device scalability and analog performance metrics are discussed. Threshold voltage (Vth), sub-threshold swing (SS), DIBL, on-state drive current (Ion), off- state leakage current (Ioff), Ion/Ioff ratio are the important Figures of Merit (FoMs) under device scalability. As far as analog circuits are concerned, the most important parameters are the transconductance (gm), output conductance (gd), intrinsic gain (AV). Fig. 2(a) and (b) describe all three important SCEs, which include the variation of Vth, SS, and DIBL for different temperatures. The threshold voltage is determined from IDS– VGS characteristics. It is considered to be that value of the VGS for which the IDS approaches 10 −6 A/μm at VDS = 0.5 V. The calculation of DIBL is done as per (2). 1 2 2 1( ) ( )th DS th th DS DSDIBL V V V V V V      (2) The Vth is observed at two different drain bias VDS1=0.5 V and VDS2=1.0V. From the Fig. 2(a) and (b), it should be noted that Vth is decreasing with an increase in temperature, but the 616 S. K. MOHAPATRA, K. P. PRADHAN, P. K. SAHU SS, and DIBL values are decreasing as temperature increases. The typical value for the SS of Multi-gate MOSFET is 60 mV/decade. According to Fig. 2(b), the SS value is lowest for T< 300 K (room temperature), then it starts increasing as temperature increases and reaches its typical value at T=300 K. The DIBL value is quite impressive throughout the entire temperature range. As there is a little variation in Vth for two different VDS at temperatures from 200 K to 400 K, so the DIBL varies from 5 mV/V to 14.38 mV/V. (a) (b) Fig. 2 (a) Vth as a function of temperature for different VDS, (b) SS and DIBL as a function of temperature for VDS=0.5 V. Fig. 3(a) and (b) show the Ion, and Ioff respectively for a wide range of temperature variations at VGS=0.5V and VDS=0.5V. The on state current (Ion) is extracted, by calculating the maximum drain current (ID) from the IDS–VGS characteristics at VGS=0.5 V and VDS=0.5 V. The off state current (Ioff) is extracted, by calculating the drain current (ID) at VGS=0 and VDS=VDD. The Ioff shows a very low value for T< 300 K and then started increasing as temperature increases; this is due to the low SS and high Vth values at low temperatures. The temperature dependence on the ID is influence by Vth as: ( ) ( )[ ( )]D GS thI T T V V T  (3) The temperature dependant ID(T) is directly related to µ(T) or VGS–Vth(T) term. So, increasing the VGS–Vth(T) term causes the ID(T) to increase because the Vth decreases with increase in temperature as shown in Fig. 3(a) and (b). (a) (b) Fig. 3 (a) On state current (Ion), (b) Off state current (Ioff), as a function of temperature for different VDS. Analysis of ZTC Point in HKMG-DG-MOSFET for Analog Application 617 The Ion/Ioff is a very important parameter for switching application; it should be very high for a good switch. According to Fig. 4(a), the Ion/Ioff is 2.3010 14 for T=100 K, then it starts falling down as temperature increases and reaches 1.2010 4 for T=400 K. At higher temperature regions, the high value of Ion because of lower Vth and the high value of Ioff due to the high SS values compensate each other and give rise to nearly constant Ion/Ioff. Fig. 4(b) shows the variation of the ID and gm with VGS for different bias temperatures. As per (2), at high gate bias the µ(T) dominates because at higher T, lattice scattering dominates and causes reduction in the channel mobility, which further reduces the ID. At low gate bias the VGSVth(T) term causes the ID to increase with increasing temperature because a low Vth is predicted at higher temperatures. These two opposite effects will cancel each other out at a value of VGS where the ID shows minimum variation with T. This point is called ZTC bias point. The gm–VGS plot can be obtained by the derivative of the ID with respect to the VGS. At VGS< Vth (channel is weakly inverted) the ID is due to diffusion. The diffusion current increases with increase in T due to hike in intrinsic carrier concentration. At VGS >Vth, gm will decrease as T increases due to mobility degradation. (a) (b) Fig. 4(a) On-off current ratio (Ion/Ioff) as a function of temperature, (b) Drain current (ID) and Transconductance (gm) as a function of VGS for different values of operating temperature. The reduction in Vth with increase in temperature will increase gm but the reduction of gm occurs due to degradation of mobility. These two phenomena will compensate each other to give rise to a ZTC bias point for gm. From the figure we can conclude that the transconductance ZTC point (0.014 V) is lower than the drain current ZTC bias point (0.552 V). The ZTCIDS and ZTCgm bias points are two important measures in analog circuit design. In OPAMP (operational amplifier) design, to maintain constant DC current levels, the devices need to be biased at ZTCIDS points, while input devices can be biased at ZTCgm point to achieve stable circuit parameters. The simulated output current (IDS) and output conductance (gd) versus drain bias (VDS) at a VGS=0.5 V for different temperatures are plotted in Fig. 5(a). Because of the above said µ(T) and Vth effects with respect to temperature, the IDS decreases as T increases below the ZTC point and the reverse is happening after the ZTC point for both parameters. The ZTC point for gd is lower than the output current ZTC point. The intrinsic gain (AV = gm/gd) is a valuable FOM for operational transconductance amplifier (OTA) and it is given in Fig. 5(b). From Fig. 5(b), high gain can be observable for high temperatures in 618 S. K. MOHAPATRA, K. P. PRADHAN, P. K. SAHU subthreshold regime and just a reverse effect in above threshold region. From this it can be concluded that the device shows better results in subthreshold regime for higher T and it is a good candidate in above threshold regime for lower T. (a) (b) Fig. 5(a) Output current (ID) and Output conductance as a function of VDS for different values operating temperature, (b) Intrinsic Gain (AV) as a function of VGS for the different values operating temperature. The important performance metrics are tabulated in Table 1. By observing the table, it is clear that our device shows very impressive values in low temperature ranges. The Ion/Ioff, SS and AV of the device increases as temperature decreases and attains their maximum values for T=100 K. Table 1 Extracted Parameters for various Temperatures Temperature in K Ion/Ioff DIBL (mV/V) SS (mV/Decade) Av in dB 400 1.2010 4 14.38 83.52 38.780 350 8.0810 4 12.52 72.83 40.514 300 1.0210 6 10.33 62.30 42.402 250 3.4510 7 7.78 51.85 44.355 200 6.5010 9 5.00 41.45 46.311 150 1.1910 13 11.75 18.80 48.248 100 2.3010 14  20.87 50.180 4. CONCLUSION The ZTC bias points of the HKMG DG-MOSFET are investigated using the 2-D numerical simulation. The results presented in this work give a detailed idea about the ZTC bias point for parameters like ID, and gm. These results provided here can serve as a good design tool for designing circuits in a wide range of temperature applications and show promising solutions to minimize temperature degradation of analog circuits. The work identified the distinct ZTC points for the device in nanoscale. Analysis of ZTC Point in HKMG-DG-MOSFET for Analog Application 619 REFERENCES [1] F. S. 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