08_494-8228-1-LE.indd FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 29, No 1, March 2016, pp. 101 - 112 DOI: 10.2298/FUEE1601101K 1University of Priština, Faculty of Technical Science, Serbia 2University of Priština, Faculty of Natural Sciences and Mathematics, Serbia 3University of Niš, Faculty of Electronic Engineering, Serbia Ivan Krstić1, Negovan Stamenković2, Vidosav Stojanović3 Binary to rnS EncodEr for thE Moduli SEt {2n – 1, 2n, 2n + 1} with EMBEddEd diMiniShEd-1 channEl for dSP aPPlication Received September 24, 2014; received in revised form September 1, 2015 corresponding author: Ivan Krstić University of Priština, Faculty of Technical Sciences, Serbia (e-mail: ivan.krstic@pr.ac.rs) facta uniVErSitatiS Series: Electronics and Energetics Vol. 28, No 4, December 2015, pp. 507 - 525 DOI: 10.2298/FUEE1504507S horiZontal currEnt BiPolar tranSiStor (hcBt) – a low-coSt, hiGh-PErforMancE flEXiBlE BicMoS tEchnoloGy for rf coMMunication aPPlicationS tomislav Suligoj1, Marko Koričić1, Josip Žilak1, hidenori Mochizuki2, So-ichi Morita2, Katsumi Shinomura2, hisaya imai2 1University of Zagreb, Faculty of Electrical Engineering and Computing, Department of Electronics, Micro- and Nano-electronics Laboratory, Croatia 2Asahi Kasei Microdevices Co. 5-4960, Nobeoka, Miyazaki, 882-0031, Japan abstract. In an overview of Horizontal Current Bipolar Transistor (HCBT) technology, the state-of-the-art integrated silicon bipolar transistors are described which exhibit fT and fmax of 51 GHz and 61 GHz and fTBVCEO product of 173 GHzV that are among the highest-performance implanted-base, silicon bipolar transistors. HBCT is integrated with CMOS in a considerably lower-cost fabrication sequence as compared to standard vertical-current bipolar transistors with only 2 or 3 additional masks and fewer process steps. Due to its specific structure, the charge sharing effect can be employed to increase BVCEO without sacrificing fT and fmax. Moreover, the electric field can be engineered just by manipulating the lithography masks achieving the high-voltage HCBTs with breakdowns up to 36 V integrated in the same process flow with high-speed devices, i.e. at zero additional costs. Double-balanced active mixer circuit is designed and fabricated in HCBT technology. The maximum IIP3 of 17.7 dBm at mixer current of 9.2 mA and conversion gain of -5 dB are achieved. Key words: BiCMOS technology, Bipolar transistors, Horizontal Current Bipolar Transistor, Radio frequency integrated circuits, Mixer, High-voltage bipolar transistors. 1. INTRODUCTION In the highly competitive wireless communication markets, the RF circuits and systems are fabricated in the technologies that are very cost-sensitive. In order to minimize the fabrication costs, the sub-10 GHz applications can be processed by using the high-volume silicon technologies. It has been identified that the optimum solution might Received March 9, 2015 corresponding author: Tomislav Suligoj University of Zagreb, Faculty of Electrical Engineering and Computing, Department of Electronics, Micro- and Nano-electronics Laboratory, Croatia (e-mail: tom@zemris.fer.hr) FACTA UNIVERSITATIS (NIŠ) SER.: ELEC. ENERG. vol. 27, no. 4, December 2014, xx-xx Binary to RNS Encoder for the Moduli Set {2n − 1,2n,2n + 1} with Embedded Diminished-1 Channel for DSP Application Ivan Krstić, Negovan Stamenković and Vidosav Stojanović Abstract: A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memoryless architecture of binary-to-RNS encoder based on the special moduli set {2n − 1,2n,2n + 1} with embedded modulo 2n + 1 channel in the diminished-1 rep- resentation is presented. Any of two channels (standard modulo 2n + 1, or modulo 2n + 1 in the diminished-1 representation) operation can be performed by using a sin- gle switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements. Keywords: RNS system, special moduli set, forward encoder, diminished-1 encoded channel, modulo carry save adders, Virtex FPGA. 1 Introduction Residue Number System [1, 2] is a non-weighted integer number system in which arithmetic operations are limited to the addition, subtraction and multiplica- tion. Other arithmetic operations such as division, sign detection, overflow, scaling Manuscript received on September 25, 2014. I. Krstić is with University of Priština, Faculty of Technical Sciences (e-mail ivan.krstic@pr.ac.rs). N. Stamenkovic is with University of Priština, Faculty of Natural Sciences and Mathematics (e-mail negovan.stamenkovic@pr.ac.rs). V. Stojanović is with University of Niš, Faculty of Electronic Engineering (e-mail vidosav.stojanovic@elfak.ni.ac.rs). 1 FACTA UNIVERSITATIS (NIŠ) SER.: ELEC. ENERG. vol. 27, no. 4, December 2014, xx-xx Binary to RNS Encoder for the Moduli Set {2n − 1,2n,2n + 1} with Embedded Diminished-1 Channel for DSP Application Ivan Krstić, Negovan Stamenković and Vidosav Stojanović Abstract: A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memoryless architecture of binary-to-RNS encoder based on the special moduli set {2n − 1,2n,2n + 1} with embedded modulo 2n + 1 channel in the diminished-1 rep- resentation is presented. Any of two channels (standard modulo 2n + 1, or modulo 2n + 1 in the diminished-1 representation) operation can be performed by using a sin- gle switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements. Keywords: RNS system, special moduli set, forward encoder, diminished-1 encoded channel, modulo carry save adders, Virtex FPGA. 1 Introduction Residue Number System [1, 2] is a non-weighted integer number system in which arithmetic operations are limited to the addition, subtraction and multiplica- tion. Other arithmetic operations such as division, sign detection, overflow, scaling Manuscript received on September 25, 2014. I. Krstić is with University of Priština, Faculty of Technical Sciences (e-mail ivan.krstic@pr.ac.rs). N. Stamenkovic is with University of Priština, Faculty of Natural Sciences and Mathematics (e-mail negovan.stamenkovic@pr.ac.rs). V. Stojanović is with University of Niš, Faculty of Electronic Engineering (e-mail vidosav.stojanovic@elfak.ni.ac.rs). 1 102 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 103 2 I. Krstić, N. Stamenković and V. Stojanović: and magnitude comparison are non-modular and quite complex for implementa- tion. The RNS is defined in terms of a set of relatively prime moduli called RNS basis. Special moduli set {2n − 1,2n,2n + 1} has gained popularity and is expected to play an important role in RNS digital signal processing [3]. In comparison with the other moduli sets, special moduli set has the advantage of low-cost forward conversion, modulo reduction, and the reverse conversion. Thus, the use of this moduli set can significantly reduce hardware complexity and delay [4]. The RNS DSP consists of three major parts: binary-to-residue encoder, mod- ular arithmetic channels and residue to binary decoder (reverse converter). The forward encoder and reverse converter are needed to achieve the RNS representa- tion of the binary number and vice versa, respectively [5]. The above-mentioned modular operations, required by each modular arithmetic channel, are inherently carry-free addition, multiplication and borrow-free subtraction, which means that each digit of the resulting number is a function of only one digit from each operand and independent of the others. This is the most attractive feature of RNS that en- ables one to design highly parallel structures for computation which leads to speed improvement required for the DSP applications [6, 7, 8, 9, 10]. A binary-to-residues encoder is an essential building block for a residue number system and as such it should be built with a minimal amount of the hardware and along with that be efficient in terms of speed and power. Conceptually, binary- to-residues encoder involves computation of the remainders of the input bit stream with respect to the each modulus in the RNS moduli set. In other words, the binary- to-residues encoder maps a binary weighted number into a finite ring [11]. A finite ring is a set of finite elements over which the modular addition and the modular multiplication operations are defined. Main parts of binary-to-residues encoder are the forward converters (residue generators). The forward converters are usually classified into the next two cate- gories: the one based on the arbitrary moduli-sets [12, 4] which are usually built using the look-up tables, and the other based on special moduli-sets [13, 14, 15]. The use of special moduli-sets simplifies the forward conversion algorithms and such forward converters can be realized using only combinational logic. The dynamic range of RNS system, which is equal to the product of the mod- ulus of three moduli-set base {2n − 1,2n,2n + 1}, is M = 23n − 2n i.e. corresponds to the 3n bits. Thus, any 3n-bit unsigned binary integer X can be uniquely repre- sented by its residues: X = (x1,x2,x3), where x1 is the reminder when X is divided by modulo 2n − 1 denoted as ⟨X⟩2n−1, x2 = ⟨X⟩2n and x3 = ⟨X⟩2n+1. The diminished-1 number system [16] can be used to represent modulo 2n + 1 residue (x3 = ⟨X⟩2n+1) as: x′3 = ⟨X − 1⟩2n+1. Thus, the each operand is represented decreased by one, and the zero operands are not used in the computation channel. 102 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 103 Binary to RNS encoder with Diminished-1 encoded Channel 3 In the diminished-1 representation, x′3 is represented as 2 nx3,n + X ′3, where x3,n is zero indication bit, and X ′3 is n-bit number part. If x ′ 3 > 0, x3,n = 0 and X ′ 3 = X3 − 1, whereas for x′3 = 0; x3,n = 1, and X ′ 3 = 0. Thus, for the diminished-1 representation, the residue of X − 1 modulo 2n + 1 instead of the residue X modulo 2n + 1 is used. The results of arithmetic operations are derived alternatively when any of operands or the result is equal to zero [17, 18, 19]. In this way, the diminished-1 representa- tion can lead to the implementations with delay and area complexity approaching that of the modulo 2n − 1 channel. This paper presents a binary-to-residues encoder based on special moduli set {2n − 1,2n,2n + 1} with embedded diminished-1 encoded channel, which unifies the encoders architectures presented in [15]. Theoretical background of forward converters for 2n −1 and 2n channel remains the same as in [15], while new forward converter for 2n + 1 channel with embedded diminished-1 encoded channel has been developed. The standard and the diminished-1 forward converters for modulo 2n + 1 channel are implemented on the same hardware. Thus, the standard 2n + 1 channel or the diminished-1 channel can be activated simply, by using the single switch. The rest of the paper is organized as follows. In Section 2 we introduce the binary-to-residues memoryless encoder for special moduli set based only on the standard combinational logic and a novel design of the binary to residue encoder with embedded diminished-1 channel. Section 3 presents the hardware implemen- tation and performance evaluation. Our conclusion is drawn in Section 4. 2 Binary-to-residues encoder In our approach, the 3n-bit input is divided into three n-bit sections to obtain the corresponding three residue numbers in parallel. An 3n-bit integer in the range 0 ≤ X ≤ M − 1 can be represented in power-of-two notation as [20, 21]: X = 3n−1 ∑ i=0 bi2 i = N2 × 22n + N1 × 2n + N0 , (1) where N0 = n−1 ∑ i=0 bi2 i, N1 = 2n−1 ∑ i=n bi2 i−n and N2 = 3n−1 ∑ i=2n bi2 i−2n . (2) In order to obtain the RNS representation of the integer X , partitioned into three n-bit parts N0, N1 and N2, three residue generators are required, one for each channel. 104 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 105 4 I. Krstić, N. Stamenković and V. Stojanović: 2.1 Forward conversion for modulo 2n and modulo 2n − 1 channel Forward conversion for modulo 2n channel is quite simple, i.e. the residue x2 can be obtained by truncation of X : x2 = ⟨X⟩2n = bn−1bn−2 ···b0 . (3) The calculation of x1 can be performed as a sequence of additions [15]: x1 = ⟨N2 + N1 + N0⟩2n−1 , (4) which can be performed by CSA with EAC (carry save adder with end around carry) on whose inputs three n-bit operands (N2, N1, N0) are connected, followed by the CPA with EAIC (carry propagate adder with end around inverted carry) and decrementer. Slight modifications to the architecture of the modulo 2n − 1 residue generator presented in [15] are introduced: LSB full-adder of CPA with EAIC (end-around inverted carry) has been replaced with HA (full-adder with one input driven by the logical one), while MSB half-subtractor of decrementer has been replaced with XOR gate, Fig. 1. HA has the same complexity as the standard half-adder except for an extra inverter, whose delay and area consumption can be ignored if using the unit-gate model as a means of performance evaluation. The critical path of the binary-to-modulo 2n − 1 converter is depicted by a dashed line. FA FA FA FA FA FA FA FA FA FA HAFA HS HS HS HS HS N2,5 N2,4 N2,3 N2,2 N2,1 N2,0 N1,5 N1,4 N1,3 N1,2 N1,1 N1,0 N0,5 N0,4 N0,3 N0,2 N0,1 N0,0 cout x1,5 x1,4 x1,3 x1,2 x1,1 x1,0 s5 s4 s3 s2 s1 s0c5 c4 c3 c2 c1 c0 Fig. 1. The architecture of the modulo (26 − 1) residue generator. Propagation delay of binary to modulo 2n − 1 converter, according to the unit- gate model, is T1 = 3n + 4. The area cost of binary to modulo 2n − 1 converter is 104 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 105 Binary to RNS encoder with Diminished-1 encoded Channel 5 A1 = 17n − 5. 2.2 Forward conversion for modulo 2n + 1 channel Modulo 2n + 1 residue and modulo 2n + 1 residue in diminished-1 number sys- tem representation can be calculated by equations derived in [15]: x3 = ⟨S +C + 1⟩2n+1 , (5) x′3 = ⟨S +C⟩2n+1 , (6) where S and C are n-bit partial sum and carry vectors generated by modulo 2n + 1 carry save adder, whose inputs are driven by N2, N1 and N0, where N1 = 2n −1−N1 is the one’s complement of operand N1 [22]. By introduction of a control bit d d = { 1, if calculating x3 0, if calculating x′3 , (7) equations (5) and (6) are combined to form x′′3 = ⟨S +C + d⟩2n+1 . (8) The modulo 2n + 1 addition of two n-bit operands S = sn−1sn−2 ...s0, C = cn−1cn−2 ...c0 and the 1-bit operand d is based on the following relation x′′3 = { S +C + d, S +C + d ≤ 2n S +C + d +(2n − 1)− 2n+1, otherwise . (9) In order to implement (9) we can ignore the output carry (cout ) from 2n+1 position and add the constant value of 2n −1 to the result of A = S+C +d (in binary notation A = anan−1 ...a0), if S + C + d > 2n. That is, the output of the residue generator should yield the value B which is obtained by adding the (n + 1)-bit binary number K = 0 11...1� �� � n to the binary number A, B = anan−1 ...a0 +0 11...1� �� � n , where an = cout . Let pi+1 denote the carry from i-th bit position obtained while performing ad- dition of the binary numbers A and K. It is obvious that: p1 = a0, pi+1 = pi ∨ ai, for i = 1, 2,..., n − 1, (10) where ∨ corresponds to the logical OR operation. 106 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 107 6 I. Krstić, N. Stamenković and V. Stojanović: Furthermore, the output vector B is: b0 = a0, bi = pi ⊕ ai, for i = 1, 2,..., n − 1, bn = pn ⊕ an . (11) According to the value of the control signal sel either A = anan−1 ...a0 or B = bnbn−1 ...b0 should be connected to the output (if sel = 0 then x′′3 = A, else x ′′ 3 = B): x′′3,k = (bk ∧ sel)∨ ( ak ∧ sel ) . (12) Considering the values of cout and pn, there are three cases to be discussed: 1. If S + C + d < 2n, that is cout = 0 and pn can be zero or one, then sel = 0, which corresponds to the binary number A at the output. 2. If S +C + d = 2n, that is cout = 1 and pn = 0, then sel = 0 and x′′3 = A. 3. If S +C +d > 2n, that is cout = 1 and pn = 1, then sel = 1, which corresponds to the binary number B at the output. According to the above discussion it can be concluded that sel = cout ∧ pn, where ∧ corresponds to the logical AND operation. Equation (12) can be simplified by putting (11) in (12): x′′3,0 = a0 ⊕ sel, x′′3,i = (sel ∧ pi)⊕ ai, for i = 1, 2,..., n − 1, x′′3,n = an ∧ pn . (13) Finally, the architecture of the binary to the modulo 2n + 1 converter with the embedded modulo 2n + 1 channel in the diminished-1 representation for n = 6 is given in the Fig. 2. Depending on the value of the control bit d, the converter gives either x3 or x′3. The critical path of the converter is depicted by the dashed line. The theoretical formula for the propagation delay, i.e. conversion time, of the binary to the modulo 2n + 1 residue generator with the embedded diminished-1 channel is T3 = 2n + 10. The area cost is equal to A3 = 18n. The validity of the modulo 2n + 1 channel and the diminished-1 encoded channel operation of the binary to residues encoder for the 16-th bit input num- ber and n = 6 is demonstrated in the following example. Let X = 54 425 = 1101 010010 011001. The carry save adder with end around inverted carry (EAIC) reduces the three 6-bit inputs N0, N1 and N2 to the two 6-bit numbers: the partial sum sequence (S) and the partial carry sequence (C) 106 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 107 Binary to RNS encoder with Diminished-1 encoded Channel 7 FA FA FA FA FA FA FA FA FA FA FA dFA N2,5 N2,4 N2,3 N2,2 N2,1 N2,0 N1,5 N1,4 N1,3 N1,2 N1,1 N1,0 N0,5 N0,4 N0,3 N0,2 N0,1 N0,0 cout x3,6 or x′3,6 x3,5 or x ′ 3,5 x3,4 or x ′ 3,4 x3,3 or x ′ 3,3 x3,2 or x ′ 3,2 x3,1 or x ′ 3,1 x3,0 or x ′ 3,0 cout s5 s4 s3 s2 s1 s0c5 c4 c3 c2 c1 c0 a5 a4 a3 a2 a1 a0p6 p5 p4 p3 p2 sel Fig. 2. The architecture of binary to modulo (26 + 1) converter with the embedded modulo (26 + 1) channel in the diminished-1 representation. For d = 1 we have x3 = ⟨X⟩26+1, but for d = 0 we have diminished-1 encoded channel x′3 = ⟨X − 1⟩26+1. N2 = 0 0 1 1 0 1 N1 = 1 0 1 1 0 1 N0 = 0 1 1 0 0 1 S = 1 1 1 0 0 1 C = 0 0 1 1 0 1 1 EAIC For d = 1 the carry input of LSB full adder of the CPA adder is equal to 1, and the CPA gives: S = 1 1 1 0 0 1 C = 0 1 1 0 1 1 d = 1 A = 1 0 1 0 1 1 0 A carry out cout = a6 = 1 is generated. Since the 6-bit vector p is equal to p = [1 1 1 1 1 1] and the sel = cout ∧ p6 = 1 (bit p6 is MSB), the output of the converter is given by: x′′3 = x3 = [0 0 1 0 1 0 0] 108 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 109 8 I. Krstić, N. Stamenković and V. Stojanović: or in the decimal notation x3 = 20, which can be verified as true. For d = 0, the CPA gives: S = 1 1 1 0 0 1 C = 0 1 1 0 1 1 A = 1 0 1 0 1 0 0 A carry out cout = a6 = 1 is generated. Since the 6-bit vector p is equal to p = [1 1 1 1 0 0] and the sel = cout ∧ p6 = 1, the output of the converter is given by: x′′3 = x ′ 3 = [0 0 1 0 0 1 1] or in the decimal notation x′3 = 19, which can be verified as true. 3 Hardware implementation and performance evaluation In this section, the propagation delay and the amount of the hardware needed for implementation of proposed encoder on an ASIC and FPGA chip, along with the comparison to the encoders presented in [15] are given. The encoder architecture shown in Fig. 3 is based on equations (3), (4) and (9). CSA with EAC CSA with EAIC CPA CPA C CS Sn nn n 1 0 sw + dcout cout cin = 1 Decrementer Selection network N2 N1 N0 n n n x1 n x3 or x′3 n + 1 x2 Fig. 3. The architecture of the new binary to residues encoder for moduli set {2n − 1,2n,2n + 1} with embedded diminished-1 channel The carry save adder with the end around carry, which is an adder on whose inputs three n-bit operands are connected, followed by the decrementer is used for the modulo 2n − 1 channel. 108 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 109 Binary to RNS encoder with Diminished-1 encoded Channel 9 By using the switch sw the modulo 2n + 1 channel in the new encoder can yield either the modulo 2n + 1 residue (x3) or the modulo 2n + 1 residue represented in diminished-1 number system (x′3), as illustrated in Fig. 3. If the carry input of the CPA is equal to 1 (sw in upper position) the output of modulo (2n + 1) channel is equal to x3. On the other side, if the carry input of the CPA is equal to 0 (sw in lower position) the output of the modulo 2n + 1 channel is equal to the modulo 2n + 1 residue in diminished-1 representation denoted as x′3. As is shown in Figure 3, the CPA is critical element in the both modulo (2n −1) and modulo (2n + 1) residue generator data paths. The encoder performance can be increased if the CPA is replaced with parallel prefix adder. In the VLSI imple- mentation, the parallel-prefix adders (or carry-tree adders) are known to have the best performance [23]. However, this performance advantage does not translate directly into an FPGA chip due to constraints on the logic block configurations and routing overhead. An FPGA chip, such as the Virtex-6, contains the number of slices, each containing a number of multiplexers, look-up tables, logic gates, flip-flops, etc. The parallel-prefix adder implementation on an FPGA chip is given in [24]. However, the implementations of the binary to residues encoder based on the parallel-prefix adders can lead to the higher hardware cost and consequently considerable the power dissipation in comparison to the carry propagate based ar- chitectures. Since the residues are computed in parallel, the propagation delay of binary to residues encoder is T = max(T1,T3). That is, if n < 6, T = 2n+10, else T = 3n+4. The area cost of binary to residues encoder is A = A1 + A3 = 35n − 5. The presented algorithms were used for the description of proposed binary to residues encoder in the VHDL hardware programming language. Complete design was implemented on the Virtex 6 XC6VCX75T FPGA chip using Xilinx ISE Design Suite 14.2 while behavioral and post-route simulation of implemented encoder was performed using ISIM simulator. The exact values of the area cost and propagation delay which relate to the ASIC and the FPGA-based implementations of the presented encoder architec- ture for different values of n, along with the comparison to architectures presented in [15], are shown in Tables 1 and 2. Table 1. ASIC implementation - performance comparison Design Delay Area Encoder [15] 3n+5 34n Encoder with D-1 channel [15] max(2n + 12,3n + 5) 37n + 7 New encoder max(2n + 10,3n + 4) 35n − 5 The encoder shown in Fig. 3 can perform the operation of the both encoders 110 I. KrstIĆ, N. stameNKovIĆ, v. stojaNovIĆ Binary to RNS Encoder with Diminished-1 Encoded Channel 111 10 I. Krstić, N. Stamenković and V. Stojanović: presented in [15]. As can be seen from Table 1 there is no significant propaga- tion delay improvement if the ASIC implementation is considered. However, the increase of performance regarding area consumption is significant in comparison to the encoder with the modulo 2n + 1 residue in the diminished-1 number system representation. Table 2. FPGA implementation - Propagation delay [ns] / Area consumption [slices] n Encoder [15] Encoder with D-1 channel [15] New encoder 4 4.072 / 28 4.034 / 29 3.885 / 31 5 4.962 / 36 4.806 / 38 4.529 / 41 6 6.238 / 45 6.099 / 47 5.370 / 48 7 7.012 / 52 8.049 / 54 6.500 / 58 8 4.463 / 74 4.567 / 77 4.618 / 77 10 5.535 / 90 5.535 / 95 5.563 / 96 Functional simulation waveforms of the binary to residues encoder based on moduli set {63,64,65} with diminished-1 encoded channel are shown in Fig. 4. The length of the input string X is 18 bits and it is sub-grouped into three groups of 6 bits. The output residues are 6 bits long for modulo 26 − 1 and modulo 26 channels, and 7 bits long for modulo 26 + 1 channel. Fig. 4. Functional simulation waveforms of the binary-to-residue encoder based on moduli set {63,64,65} with diminished-1 encoded channel. 4 Conclusion In this paper, we investigated the binary to residues memoryless encoder, which is an important issue concerning the utilization of the RNS number system in DSP application. We proposed a new binary to residues encoder for moduli set {2n − 1,2n,2n + 1} with embedded diminished-1 channel which can be used instead of standard modulo 2n + 1 channel. The modulo 2n + 1 channel and the diminished- 1 channel are implemented on the same hardware and the encoder can be used to perform either the modulo 2n + 1 or the diminished-1 channel operation. The single switch is used for the channel selection. Our approach avoids the initial 110 I. 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