FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 32, N o 4, December 2019, pp. 601-613 https://doi.org/10.2298/FUEE1904601T © 2019 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND NOVEL SINGLE LAYER FAULT TOLERANCE RCA CONSTRUCTION FOR QCA TECHNOLOGY Zahra Taheri, Abdalhossein Rezai, Hamid Rashidi ACECR Institute of Higher Education, Isfahan Branch, Isfahan, Iran Abstract. Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCADesigner tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time. Key words: Nanoelectronics, fault-tolerance, majority gate, QCA FA, ripple carry adder, quantum-dot cellular automata 1. INTRODUCTION The QCA technology is a promising computing paradigm that has widespread applications in emerging technologies like Carbon Nano Tube Field Effect Transistor (CNTFET) [1, 2, 3] and Silicon On Insulator (SOI) [4, 5]. In addition, it has the capability to provide better performance compared to other technologies such as conventional CMOS technology [6]. The QCA technology was addressed for the first time by Lent et al. [7]. This technology presents a novel computation and information transformation method [8, 9, 10]. The four-dot square cell is the fundamental unit in the QCA technology, which contains two free electrons [9, 11, 12]. Thus, there exist two stable arrangements for QCA cell. These two arrangements are denoted as cell polarization. Interconnection among the electrons of intercell can make logic ‘1’ and logic ‘0’. So, the logical states can be computed with the charge configuration of the QCA cell [8, 13]. The basic components in this technology are QCA Majority Gate (MG), QCA Inverter Gate (IG) and QCA wire [9, 14]. This technology has received extensive attention due to the immense practical Received March 21, 2019; received in revised form June 18, 2019 Corresponding author: Abdalhossein Rezai ACECR Institute of Higher Education, Isfahan Branch, Isfahan, Iran (E-mail: rezaie@acecr.ac.ir)  602 Z. TAHERI, A. REZAI applications such as QCA multiplexer [8, 9, 11], QCA multiplier [15], efficient design of QCA Full Adder (FA) [10, 15-35], comparator [14, 36] and shift register [37]. On the other hand, the FA circuit is an inseparable component in the computer arithmetic circuits. Hence, efficient QCA FA construction design is an interesting research topic. The 1-bit QCA FA construction can be designed by employing MG and IG in the QCA technology [10]. The QCA Fault Tolerance (FT) circuit design is also an interesting and necessary in the QCA technology [38-47]. Hence, in order to present the developed digital circuits for future modern computing, many researchers have worked on the characteristics of FT in the QCA full adder constructions. In this paper, novel 3-input MG is proposed to offer high fault tolerance for double and single missing cell defects. Next, a novel 1-bit FT QCA FA circuit is developed using the developed 3-input MG. In addition, novel 4-bit FT QCA RCA construction is designed using the developed 1-bit FT QCA FA. The developed QCA constructions are implemented with QCADesigner tool version 2.0.3. The simulation results confirm that the developed QCA constructions have considerable advantages compared to other designs.The paper progresses as follows: In section 2, an overview of the QCA technology is presented. Then, the proposed design for new 3-input FT MG, 1-bit QCA FT FA construction, and 4-bit QCA FT RCA construction are presented in section 3. The simulation results and comparison with related works are discussed in section 4. Finally, conclusion is given in section 5. 2. BACKGROUND 2.1. QCA cell The four-dot squared cell is the fundamental unit in the QCA technology, which contains two free electrons [6]. These electrons occupy two of these four quantum dots due to electrostatic repulsion and diagonally occupy corners of the cell [18]. Thus, there exist two stable arrangements for QCA cell, which are shown in Fig. 1 [9]. These two arrangements are denoted as cell polarization. Interconnection among the electrons of intercell can be shown as logic ‘1’ and logic ‘0’. The logical state in this construction is defined by using the electrons position in quantum dots [20]. Fig. 1 The polarizations of the QCA cell [9] Novel Single Layer Fault Tolerance RCA Construction for QCA Technology 603 2.2. The QCA gates The MG, XOR and the IG are indispensable building blocks of QCA circuits [48]. Fig. 2 shows a 3-input MG, an IG and XOR gate [12, 48]. Fig. 2 The basic gates in the QCA technology (a) majority gate, (b) inverter gate, (c) exclusive-OR gate [12, 48] The 3-input MG logical function is defined as follows [11]: M (A, B, C) = BA + CA + BC (1) The majority gates can work as 2-input OR gates or 2-input AND gates by applying 1 or -1 to one of the inputs, respectively [8]. 2.3. The QCA FA The full adder is an important part of computer arithmetic circuits. If we have A, B, and Cin as the inputs, and Carry and Sum as the outputs of 1-bit full adder, the Sum and the Carry outputs can be computed as follows [20]: in in in C Maj 3(A,B,C ) AB+AC +BCout   (2) SUM = (3) 2.4. Defect in QCA circuits As it is shown in Fig. 3, the defects can be occurred during positioning of the cells to a surface or synthesis in cellular layout of the QCA circuits [29]. In generally, they can be categorized as follows:  Cell omission (missing cell): In this case, the location of the QCA cell is changed from its original position [44, 45]. The cell omission is displayed in Fig. 3(b).  Cell displacement: In this case, the QCA cell lost its original direction [41]. The cell displacement defect is displayed in Fig. 3(c).  Cell misalignment: In this case, the faults are occurred where the QCA cells are shifted from their intended locations [45]. The cell misalignment is displayed in Fig. 3(d). 604 Z. TAHERI, A. REZAI  Extra (additional) cell: In this case, an extra cell is erroneously deposited on the substrate [29]. The extra cell defect is displayed in Fig. 3(e).  Cell dislocation or cell rotation: This fault is occurred where QCA cells are rotated proportionate to the other cells in the array [40, 46]. Fig. 3(f) shows this defect. Fig. 3 Defects in the QCA circuits, (a) Fault-free majority gate, (b) Cell omission, (c) Cell displacement, (d) Cell misalignment, (e) Extra cell, (f) Rotation defect [29] 2.5 Related works A majority gate is a vital component for 1-bit QCA full adder constructions. Hence, previous MGs and 1-bit QCA constructions are reviewed in this section. Note that, the fault tolerance is calculated as follows [42]: Based on (4), the maximum fault tolerance in terms of the single missing cell defects is 20% for the conventional MG [42]. Fig. 4 shows the MG construction in [47], with 3×3 tile. Fig. 4 The utilized MG in [47] This design has 13 QCA cells. The correct function is 16.67% and 55.6% in terms of the double and single cell missing defects, respectively. Fig. 5 shows the utilized MG in [42] with 3 × 5 tile. This construction has 19 QCA cells. The number of the correct outputs of this MG is 9 cases out of 15 cases in single cell omission. As a result, it achieves 60% fault tolerance. Fault Tolera ce (%) = Number of wrong output patterns Number of detect ve patterns ×100 (4) Novel Single Layer Fault Tolerance RCA Construction for QCA Technology 605 Fig. 5 The utilized MG in [42] The number of the correct outputs in this MG is 33 cases out of 105 cases in double cell omission. As a result, it achieves 31.4% fault tolerance. On the other hand, the full adder is an important component in the construction of digital circuits. Roohi et al. [12] have presented 1-bit FT FA by using one 5-input MG, one 3-input MG, and one inverter gate. The percentage of the fault tolerance for the sum and carry outputs are 22.22% and 72.22%, respectively in [12]. This 1-bit FT FA has 0.01 µm2 area, 23 QCA cells and three clock phases delay. Cho and Swartzlander [17] have presented 1-bit FA that utilizes three MGs and two IGs. This 1-bit FT FA has 0.09 µm2 area, and four clock phases delay. The fault tolerance for the sum and carry outputs are 32% and 60.49%, respectively in [17]. Du et al. [42] have presented 1-bit FT FA that utilizes one 3-input FT MG, one 5-input MG and one inverter gate. The fault tolerance of the sum and carry outputs are 29.92% and 94.87%, respectively in [42]. The area is 0.08 µm2 and delay is two clock phases. Kassa and Nagaria [25] have presented 1-bit FA that utilizes one 3-input MG, one 5-input MG and one IG. This 1-bit FA has 0.05 µm2 area, 48 QCA cells and three clock phases delay. The fault tolerance for the sum output and carry output are 17.94% and 92.30%, respectively in [25]. Hayati and Rezaei [21] have proposed 1-bit FA that utilizes three 3-input MGs and one IG. This 1-bit FA has 0.02 µm2 area, 38 QCA cells and two clock phases delay. The fault tolerance for the sum output and the carry output are 12.12% and 48.48%, respectively in [21]. Kianpour et al. [22] have presented 1-bit FA that utilizes three 3-input MGs and one IG. This 1-bit FA has 0.07 µm2 area, 69 cells and three clock phases delay. The fault tolerance for the sum and carry outputs are 12.70% and 71.43%, respectively in [22]. Tougaw and Lent [34] have presented a 1-bit FA that utilizes five 3-input MGs and three inverter gates. This 1-bit FA has 0.2 µm2 area, 192 cells and five clock phases delay. The fault tolerance for the sum output and carry output are 34.78% and 60%, respectively in [34]. Sen et al. [23] have presented a 1-bit FA that has 0.01 µm2 area, 31 cells and two clock phases delay. The fault tolerance for the sum output and carry output are 11.54% and 76.92%, respectively in [23]. Angizi et al. [31] have presented a 1-bit FA that utilizes one 3-input MG, one 5- input MG and one IG. This 1-bit FA has 0.09 µm2 area, 95 cells and five clock phases delay. The fault tolerance for the sum output is 25.55% and for carry output is 74.44%. 606 Z. TAHERI, A. REZAI 3. THE DEVELOPED CONSTRUCTIONS This section designs a new FT MG as a basic module. Then, a novel 1-bit FT QCA FA and 4-bit FT QCA RCA constructions are implemented using this novel FT MG. 3.1. The proposed FT MG The proposed construction for the 3-input FT MG is shown in Fig. 6. In this construction, the inputs are denoted by A, B and C, and the output is denoted by Out. The output of the proposed construction is determined as follows [20]: Out = M (A, B, C) = BA + CA + BC (5) In addition, Table 1 shows truth table of the developed 3-input FT MG. Fig. 6 The proposed 3-input FT MG (a) QCA layout (b) logic diagram Table 1 Truth table of the proposed FT 3-input MG The layout of the proposed 3-input FT MG consists of 20 QCA cells. It also has 0.02 μm2 area with a 4×4 tile. 3.2. The developed 1-bit FT QCA FA construction The logical design and layout of the developed 1-bit QCA FT full adder that uses the proposed 3-input FT MG and a 3-input XOR gate as building block, are shown in Fig. 7. A B C Out 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Novel Single Layer Fault Tolerance RCA Construction for QCA Technology 607 Fig. 7 The proposed 1-bit QCA FT FA (a) QCA layout, (b) logic diagram As it shown in Fig. 7, the inputs are labeled as A, B and Cin and the outputs are shown by Sum and Cout. The proposed 1-bit QCA FT full adder takes two clock phases to generate the Sum function. The layout of the proposed 1-bit QCA FT full adder includes 44 QCA cells and its occupied area is 0.04 μm 2 . 3.3. The proposed 4-bit QCA FT RCA The logical design and layout of the proposed 4-bit QCA FT RCA are shown in Fig. 8. As shown in Fig. 8, the developed 4-bit QCA FT RCA uses four 1-bit QCA FT full adder modules that is developed in this paper. Fig. 8 The proposed 4-bit QCA FT RCA, (a) QCA layout, (b) logic diagram As it shown in Fig. 8, the inputs are labeled as A (A0, A1, A2, A3), B (B0, B1, B2, B3) and Cin and the outputs are shown by Sum (S0, S1, S2, S3) and Cout. The developed 4-bit QCA FT full adder takes four clock phases to generate the Sum function. The layout of the proposed 4-bit QCA FT RCA consists of 236 QCA cells and its occupied area is 0.49 μm2. 608 Z. TAHERI, A. REZAI 4. SIMULATION RESULTS AND COMPARISON This section presents simulation results and comparison of the proposed FT constructions. The QCADesigner tool version 2.0.3 has been utilized to simulate the proposed constructions. 4.1. The proposed 3-input FT MG Fig. 9 shows the simulation results of the proposed 3-input FT MG. To fair comparison, the layout of the proposed 3-input FT MG is re-plotted in Fig. 10 in which the QCA cells are shown by number. Fig. 9 The output waveform of the designed 3-input FT MG Fig. 10 The proposed MG with cell number Table 2 shows the simulation results of the 3-input FT MG in terms of the single missing defect. The correct functions and the fault tolerance of the various constructions for the double and single cell missing defects are comparison in Table 3. Table 2 Single missing cell defect in the proposed 3-input FT MG Novel Single Layer Fault Tolerance RCA Construction for QCA Technology 609 Table 3 The comparative table for the MG for double and single cell missing defects Based on our obtained results that are shown in tables 2 and 3, and Fig. 10, the fault tolerance of the proposed 3-input MG is 62.5% in terms of the single cell missing defect and 37.5% for the double cell missing defect. As a result, the fault tolerance for the double and single cell missing in the proposed 3-input MG are improved compared to MG in [42, 47]. 4.2. The developed 1-bit QCA FT FA The output waveform of the developed 1-bit QCA FT FA are shown in Fig. 11. Fig. 11 The output waveform of the developed 1-bit FT QCA FA The carry output and sum output fault tolerance of the developed 1-bit QCA FT FA are 84.6% and 56.4%, respectively. In addition, the area is 0.04 µm2 and delay is two Defect cell Result Defect cell Result 1 M(A, B, C) = Correct 9 M(A, B, C) = Correct 2 M(A, B', C) = Incorrect 10 M(A, B, C) = Correct 3 M(A, B, C) = Correct 11 M(A, B, C) = Correct 4 M(A, B, C) = Correct 12 M(A, B, C) = Correct 5 M(A', B, C) = Incorrect 13 M(A, B, C) = Correct 6 C = Incorrect 14 M(A, B, C') = Incorrect 7 C = Incorrect 15 M(A, B, C) = Correct 8 M(A', B', C') = Incorrect 16 M(A, B, C) = Correct Reference (3 × 3-based MG) [47] (3 × 5-based MG) [42] This paper One cell missing Two cells missing One cell missing Two cells missing One cell missing Two cells missing M(A, B, C) 5 6 9 33 10 45 Total 9 36 15 105 16 120 Fault Tolerance (%) 55.6% 16.67% 60% 31.4% 62.5% 37.5% 610 Z. TAHERI, A. REZAI clock phases. Table 4 shows the comparison of the 1-bit QCA FT FA constructers. The cost is calculated as follows: Cost=Area (μm2) × Delay (clock phase) (6) The comparison results between the proposed 1-bit QCA FT FA and other 1-bit QCA FA constructions show that although fault tolerance of the carry output in our design is lesser than the fault tolerance of the carry output in [42, 25], but the fault tolerance of the sum output in the proposed 1-bit QCA FT FA has improved compared to [42, 25]. In addition, the proposed 1-bit QCA FT FA has significant improvement in comparison with [42] in terms of area, and cost by about 50% and 50%, respectively. It should be mentioned that the percentage improvement is calculated as follows: rove e t (%) = (1 our mp ement on resu t prev ous mp ement on resu t )× 100 (7) Table 4 Comparative table for 1-bit QCA FA 4.3. The developed 4-bit QCA FT RCA Fig. 12 indicates the output waveform of the proposed 4-bit QCA FT RCA. For optimum layout, the layout of the proposed 4-bit QCA FT RCA is implemented in only one layer using 236 QCA cells and 0.49 μm 2 area. It also takes four clock phases to generate the outputs. Fig. 12 Simulation results for the proposed 4-bit QCA FT RCA In order to present a fair comparison, we have compared the proposed 4-bit FT QCA RCA with the existing designs in [12, 17, 32, 33, 42] in terms of the clock phase, occupied area, number of QCA cells and fault tolerance in Table 5. Reference [12] [17] [42] [25] [21] [22] [34] [23] [31] This paper Fault Tolerance (%) sum 22.22 32.00 26.92 17.94 12.12 12.70 34.78 11.54 25.55 56.4 carry 72.22 60.49 94.87 92.30 48.48 71.43 60.00 76.92 74.44 84.6 Area 0.01 0.09 0.08 0.04 0.02 0.09 0.20 0.01 0.09 0.04 Delay (clock phase) 3 3 2 2 2 4 5 2 5 2 Cost (Delay ×Area) 0.03 0.36 0.16 0.08 0.04 0.36 1 0.02 0.45 0.08 Novel Single Layer Fault Tolerance RCA Construction for QCA Technology 611 Based on these results, our design provides a significant reduction on resulting the clock delay, area, number of QCA cells and fault tolerance compared to previous designs in [12, 17, 23, 32, 33, 42]. Moreover, the proposed constructions have significant robustness against the missing cell defects. They can achieve to higher level of fault tolerance. According to equation (8), the 4-bit QCA RCA has approximately 45.2% and 42.8% improvements compared to the presented 4-bit QCA RCA in [42] in terms of the number of QCA cells and clock delay, respectively. Table 5 Comparative table for 4-bit QCA RCAs 5. CONCLUSIONS This paper presented and evaluated an efficient 3-input FT MG. The fault tolerance of the proposed 3-input MG has investigated for double and single missing cell defects and compared to previous works. Then, the 1-bit FA and 4-bit RCA have been designed. The developed designs are simulated using QCADesigner tool version 2.0.3. Our simulation results confirm that the proposed 3-input FT MG could reach 62.5% fault tolerance for the single cell missing defect and 37.5% fault tolerance for the double cell missing defect. The proposed 1-bit QCA FT full adder could reach 84.6% and 56.4% fault tolerance for carry output and sum output, respectively. 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