FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 34, No 1, March 2021, pp. 105-114 https://doi.org/10.2298/FUEE2101105R © 2021 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND Original scientific paper DESIGN OF NOVEL MULTIPLEXER CIRCUITS IN QCA NANOCOMPUTING Hamid Rashidi, Abdalhossein Rezai ACECR Institute of Higher Education, Isfahan Branch, Isfahan, Iran, Abstract. Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilize 16 (0.01μm2), 96 (0.11μm2), and 286 (0.43μm2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%- 99% compared to the existing multiplexer circuits. Key words: Multiplexer circuit, Quantum-dot cellular automata; coplanar, nanotechnology, nanoelectronics 1. INTRODUCTION Quantum-dot Cellular Automata (QCA) is one of the technologies at nano-scale level, which is developed by Lent et al. [1] in 1993. The QCA technology can be used for maintaining the trend predicted by Moore’s law [2]. This technology has many advantages such as high device density, high switching speed, and low power consumption in comparison with Complementary Metal-Oxide-Semiconductor (CMOS) technology [3]. Basic devices in this technology consist of QCA cells, wire crossing and QCA logic gates. The fundamental unit in the QCA technology is the QCA cell that is comprised of a square with 4 quantum dots in corners [1, 4]. It should be noted that each QCA cell has only two electrons that can tunnel through neighboring dots. These two electrons are resided in opposite corners. So, there are two possible polarizations. Fig. 1 shows these two kinds of polarization, P= -1 and P=+ of QCA cells [5]. Received July 30, 2020; received in revised form October 10, 2020 Corresponding author: Abdalhossein Rezai ACECR Institute of Higher Education, Isfahan, Iran E-mail: rezaie@acecr.ac.ir 106 Z. TAHERI, A. REZAI Fig. 1 Two possible polarizations in QCA cells, P= -1 and P=+1[5] QCA wires consist of a number of QCA cells which can be used for transferring input cell polarization [5]. QCA wires can be categorized in two groups: (a) single layer crossing wire, and (b) multilayer crossing wire. In addition, A four-phase (four-zone) clock pulse provided synchronization of information flow in the QCA circuits. The QCA clock pulse is employed to reduce power dissipation [3, 6]. The QCA cells behave like a single latch in each clock phase and propagate information in the same direction. As illustrated in Fig. 2, the QCA clock is composed of four phases and each phase is shifted by 90 degrees [3, 6]. In the clock phase, a signal has four states: 1) Low-to-high state (SWITCH phase), 2) High state (HOLD phase), 3) High-to-low (RELEASE phase), 4) Low state (RELAX phase). Fig. 2 Four phases of the QCA [3, 6] Design Of Novel Multiplexer Circuits in QCA nanocomputing 107 When the QCA clock is in the low-to-high state, the potential energy of the QCA cell is low. So, tunneling barriers of the QCA cell start to raise and their polarizations start to actual computation according to the state of their neighboring cells during switch phase. The potential barriers of the QCA cells are in the highest level and they avoid electrons from tunneling in the hold phase. During the release phase, the reduction in the cell polarization is started and the tunneling barriers gradually are reduced. Finally, in the relax phase, the cells stay in an unpolarized state when potential barriers are held in low state and no barrier exists between the dots. The overall delay of the QCA circuits can be specified by the number of critical path clock phase [3]. In QCA circuits basic logic units are Majority Voter Gate (MVG) and inverter gate [1]. The 3-input MVG is considered as the most important gate in the QCA technology. It is because the 2-input OR gate and 2-input AND gate can be constructed using MVG by fixing one of the three inputs to P= +1 or P= -1, respectively [6]. The logic function of the MVG can be defined by the following equation: Maj (A, B, C) = Out = AB + BC + CA (1) Where A, B, and C are inputs and the output is displayed by Out. A four-phase clock pulse provides synchronization of information flow in the QCA circuits [7]. In addition, the QCA clock is employed for reducing the power dissipation [8]. The QCA cells behave similarly to a single latch in each clock phase. So, the information is propagated in the same direction. In recent years, many different logic circuits have been developed in the QCA technology for various applications, such as QCA multiplier [9], QCA full adder [5, 10], QCA multiplexer [3, 6-9, 11-15], QCA counter [16], QCA shift register [17], and QCA comparator [18, 19]. In addition, multiplexer circuits play a significant role in the digital circuit design such as arithmetic logic unit design [6]. In this study, we develop a circuit with the aim of improving the performance of the single-layer 2 to 1 QCA multiplexer. Then, efficient and single-layer 4 to 1 and 8 to 1 multiplexer circuits are implemented based on this 2 to 1 multiplexer. 2. DESIGN OF 2 TO 1 QCA MULTIPLEXER The developed 2 to 1 QCA multiplexer is shown in Fig. 3. This circuit consists of one inverter gate, one Rotate Majority Voter Gate (RMVG) and two Original Majority Voter Gates (OMVGs) due to area efficiency and need to have suitable architecture for modular design methodology for constructing efficient 2n to 1 multiplexer circuits. This circuit consists of two inputs, A and B, one address line, S, and one output, F. The output F is expressed by the following equation: F = A. S̅ + B. S (2) 108 Z. TAHERI, A. REZAI Fig. 3 The developed 2 to 1 QCA multiplexer circuit (a) logical circuit, (b) layout To verify and justify the layout of the developed single layer 2 to 1 QCA multiplexer, QCADesigner tool version 2.0.3 [20] is utilized as a simulator on the cell level for QCA circuits. Figure 4 shows the simulated waveform of the developed 2 to 1 multiplexer circuit. Fig. 4 The waveform of the developed 2 to 1 multiplexer circuit It should be mentioned that for rapid access to simulation results, bi-stable approximation simulation engine has been chosen. For optimum layout, cellular layout of the developed 2 to 1 multiplexer is designed in one layer using 16 QCA cells and an area of 0.01 μm2. It also takes 0.5 clock cycles to generate the output. Table 1 summarizes comprehensive comparison between the developed single layer 2 to 1 QCA multiplexer circuit and other circuits in [3, 6-8, 13, 14] with regard to the latency Design Of Novel Multiplexer Circuits in QCA nanocomputing 109 (required clock cycles), cell count, circuit area (µm2), and cost, where the cost is defined by following equation: cost = Area × Latency2 (3) Table 1 The simulation results of the single-layer 2 to 1 multiplexer circuits Reference Number of cells Area (µm2) Latency Cost [14] 27 0.03 0.75 0.0169 [13] 19 0.02 0.75 0.0113 [7] 26 0.02 0.5 0.005 [6] 19 0.02 0.5 0.005 [8] 23 0.02 0.5 0.005 [15] 24 0.02 0.75 0.0113 [3] 15 0.01 0.5 0.0025 This paper 16 0.01 0.5 0.0025 Based on these simulation results, the developed 2 to 1 multiplexer circuit has an improvement with regard to cost, cell count, latency and circuit area compared to other 2 to 1 QCA multiplexer circuits in [13, 14, 15]. Moreover, our developed circuit has advantages with regard to cost, cell count, and circuit area compared to 2 to 1 QCA multiplexer circuits in [6-8]. The results demonstrate that the proposed 2 to 1 multiplexer circuit reduced the cost by about 50%-85% compared to the circuits that are proposed in [6-8, 13-15]. Although the 2 to 1 multiplexer circuit in [3] has advantages compared to our developed 2 to 1 multiplexer, the architecture of the developed 2 to 1 multiplexer is such that it is suitable for modular design methodology for constructing efficient 2n to 1 multiplexer circuits. 3. DESIGN OF 4 TO 1 QCA MULTIPLEXER The developed single-layer 4 to 1 QCA multiplexer circuit is shown in Fig. 5, which utilizes three developed 2 to 1 QCA multiplexer modules. Fig. 5 The developed single-layer 4 to 1 QCA multiplexer circuit (a) layout, (b) logic circuit 110 Z. TAHERI, A. REZAI The developed circuit consists of two address lines, four inputs, and one output. A, B, C, and D are utilized as input signals, S0 and S1 denote the address lines and output signal is shown by F. The output F is expressed by following equation: 𝐹 = (𝑆1. 𝑆0)𝐷 + (𝑆1.𝑆̅0)𝐶 + (𝑆̅1. 𝑆0)𝐵 + (𝑆̅1.𝑆̅0)𝐴 (4) Figure 6 shows the simulated waveform of the developed 4 to 1 multiplexer design. Fig. 6 The waveform of the developed 4 to 1 multiplexer design For optimum layout, the cellular layout of the developed 4 to 1 multiplexer is designed in one layer using 96 QCA cells and an area of 0.11 μm2. It also takes 1 clock cycle to generate the output. Table 2 summarizes comprehensive comparison between the developed single-layer 4 to 1 QCA multiplexer circuit and previous 4 to 1 QCA multiplexer circuits in [3, 7, 8, 11, 12]. Table 2 The simulation results for the 4 to 1 QCA multiplexer circuits Reference Number of cells Area (µm2) Latency Cost [7] 271 0.37 4.75 8.3481 [11]* 251 0.2 1.25 0.3125 [11] 199 0.27 1.50 0.6075 [8] 155 0.24 1.25 0.375 [12]* 103 0.08 1.75 0.245 [3] 107 0.15 1 0.15 This paper 96 0.11 1 0.11 * multilayer Based on these simulation results, the developed 4 to 1 QCA multiplexer circuit has advantages with regard to cost, cell count, latency, and circuit area compared to other 4 to 1 QCA multiplexer circuits in [7, 8, 11, 12]. Our developed 4 to 1 multiplexer circuit provides an improvement in terms of cost, number of cells, and circuit area compared to 4 to 1 QCA multiplexer circuit in [3]. The developed circuit also provides an improvement in comparison with 4 to 1 QCA multiplexer circuit in [12] with regard to cost, cell count Design Of Novel Multiplexer Circuits in QCA nanocomputing 111 and latency. The results demonstrate that the proposed 4 to 1 multiplexer circuit reduces the cost by about 26%-98% compared to the circuits that are proposed in [3, 7, 8, 11, 12]. 4. DESIGN OF 8 TO 1 QCA MULTIPLEXER The developed single-layer 8 to 1 QCA multiplexer circuit is displayed in Fig. 7, which utilizes the developed 2 to 1 multiplexer circuit and two developed 4 to 1 QCA multiplexer circuits. The developed circuit consists of eight inputs, one output, and three address lines. A, B, C, D, E, F, G, and H are utilized as input signals, S0, S1, and S2 denote the address lines and output signal is shown by Out. The output Out, is expressed by the following equation: Out=(S2.S1.S0)H+(S2.S1.S ̅0)G+(S2.S ̅1.S0)F+(S2.S ̅1.S ̅0)E+(S ̅2.S1.S0)D +(S ̅2.S1.S ̅0)C+(S ̅2.S ̅1.S0)B+(S ̅2.S ̅1.S ̅0)A (5) Fig. 7 The developed single-layer 8 to 1 multiplexer circuit 112 Z. TAHERI, A. REZAI Figure 8 shows the simulated waveform of the developed 8 to 1 multiplexer design. Fig. 8 The waveform of the developed 8 to 1 multiplexer design For optimum layout, QCA layout of the developed 8 to 1 multiplexer is designed in one layer using 286 QCA cells and an area of 0.43 μm2. It also takes 1.5 clock cycles to generate the output. Table 3 summarizes comprehensive comparison between the developed single- layer 8 to 1 multiplexer circuit and previous 8 to 1 QCA multiplexer circuits in [3, 7, 8, 11]. Table 3 The simulation results for the 8 to 1 QCA multiplexer circuits Based on these simulation results, the developed 8 to 1 QCA multiplexer circuit has advantages with regard to cost, cell count, latency and circuit area compared to other 8 to 1 QCA multiplexer circuits in [7, 8, 11]. Moreover, our developed circuit has advantages with regard to cost, cell count, and circuit area compared to 8 to 1 QCA multiplexer circuit in [3]. The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%-99% compared to the circuits that are proposed in [3, 7, 8, 11]. Reference Number of cells Area (µm2) Latency Cost [7] 1312 1.83 10.5 201.76 [8] 462 0.87 1.75 2.67 [11] 494 0.58 2.25 2.94 [3] 293 0.58 1.5 1.31 This paper 286 0.43 1.5 0.97 Design Of Novel Multiplexer Circuits in QCA nanocomputing 113 5. CONCLUSIONS There are several kinds of nanotechnologies that are developed for replacing conventional CMOS technology [21-23]. The QCA technology is one of these nanotechnologies that provide the promising advantages. In this study, we have developed a novel and efficient single-layer circuit for 2 to 1 QCA multiplexer based on majority and inverter gates. Then, using this 2 to 1 QCA multiplexer circuit, the 4 to 1 and 8 to 1 QCA multiplexer circuits are developed. The developed circuits for QCA multiplexers have been simulated using QCADesigner 2.0.3. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilized 16 (0.01μm2), 96 (0.11μm2), and 286 (0.43μm2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%- 99% compared to the circuits that are proposed in [3, 7, 8, 11]. REFERENCES [1] C.S. Lent, P.D. Tougaw, W. Porod et al. "Quantum cellular automata", Nanotechnology, Vol. 4, No. 1, pp. 49–57, 1993. [2] J.D. Meindl, "Beyond Moore’s Law: the interconnect era", Comput. Sci. Eng., vol. 5, no. 1, pp. 20–24, 2003. [3] H. Rashidi, A. Rezai and S. Soltany, "High-performance multiplexer architecture for quantum-dot cellular automata", J. Comput. Electron., vol. 15, no. 3, pp. 968–981, 2016. [4] Z. Taheri, A. Rezai, and H. Rashidi, "Novel single layer fault tolerance RCA construction for QCA technology", FU Elec. Energ., vol. 32, no. 4, pp. 601-613, 2019. [5] D. Mokhtari, A. Rezai, H. Rashidi, F. Rabiei, S. Emadi and A. Karimi, "Design of novel efficient full adder circuit for quantum-dot cellular automata technology", FU Elec. Energ., vol. 31, no. 2, pp. 279-285, 2018. [6] B. Sen, M. Dutta, M. Goswami and B. K. Sikdar, "Modular design of testable reversible ALU by QCA multiplexer with increase in programmability", Microelectronics J., vol. 45, no. 11, pp. 1522–1532, 2014. [7] R. Sabbaghi-Nadooshan and M. Kianpour, "A novel QCA implementation of MUX-based universal shift register", J. Comput. Electron., vol. 13, pp. 1–13, 2013. [8] B. Sen, M. Goswami, S. Mazumdar and B.K. Sikdar, "Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers", Comput. Electr. Eng., vol. 45, pp. 42–54, 2015. [9] J.D. Wood and D. Tougaw, "Matrix multiplication using quantum-dot cellular automata to implement conventional micro-electronics", IEEE Trans. Nanotechnol., vol. 10, no. 5, pp. 1036–1042, 2011. [10] M. Hayati, and A. Rezaei "Design of novel efficient adder and subtractor for quantum-dot cellular automata", Int. J. Circ. Theor. Appl., vol. 43, no. 10, pp. 1446–1454, 2015. [11] G. Cocorullo, P. Corsonello, F. Frustaci and S. Perri, "Design of efficient QCA multiplexers", Int. J. Circ. Theor. Appl., vol. 44, no. 3, pp. 602–615, 2016. [12] B. Sen, A. Nag, A. De and B.K. Sikdar "Towards the hierarchical design of multilayer QCA logic circuit", J. Comput. Sci., vol. 11, pp. 233–244, 2015. [13] B. Sen, M. Dutta, D. Saran and B.K. Sikdar, "An efficient multiplexer in quantum-dot cellular automata", In Proceedings of the Progress in VLSI Design and Test, Lecture Notes in Computer Science, vol. 7373, 2012, pp. 350-351. [14] A. Roohi, H. Khademolhosseini, S. Sayedsalehi, and K. Navi, "A novel architecture for quantum-dot cellular automata multiplexer", Int. J. Comput. Sci., vol. 8, pp. 55–60, 2011. [15] R. Singh and D. K. Sharma, "Design of efficient multilayer RAM cell in QCA framework", Circuit World, vol. 47, no. 1, pp. 31-41, 2020. [16] M. N. Divshali, A. Rezai and S.S.F. Hamidpour, "Design of novel coplanar counter circuit in quantum-dot cellular automata technology", Int. J. Theor. Phys., vol. 58, no. 8, pp. 2677–2691, 2019. [17] M. N. Divshali, A. Rezai and A. Karimi, "Towards multilayer QCA SISO shift register based on efficient D-FF circuits", Int. J. Theor. Phys., vol. 57, no. 11, pp. 3326–3339, 2018. [18] A. Shiri, A. Rezai and H. Mahmoodian, "Design of efficient coplanar 1-bit comparator circuit in QCA technology", FU Elec. Energ., vol. 32, no. 1, pp. 119-128, 2019. [19] R. Mokhtarii and A. Rezai, "Investigation and design of novel comparator in quantum-dot cellular automata technology", J. Nano-Electron. Phys., vol. 10, no. 5, pp. 50141-50144, 2018. [20] K. Walus, T. Dysart, G.A. Jullien and R. Budiman, "QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata", IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 26–31, 2004. 114 Z. TAHERI, A. REZAI [21] A. Naderi, and M. Ghodrati, "Improving band-to-band tunneling in a tunneling carbon nanotube field effect transistor by multi-level development of impurities in the drain region", Eur. Phys. J. Plus, vol. 132, no. 12, p. 510, 2017. [22] A. Naderi and B. Tahne, "Methods in improving the performance of carbon nanotube field effect transistors", ECS J. Solid-State Sci. Technol., vol. 5, no. 12, pp. M131-M140, 2016. [23] A. Naderi and F. Heirani, "Improvement in the performance of SOI-MESFETs by T-shaped oxide part at channel region: DC and RF characteristics", Superlattices and Microstructures, vol. 111, pp. 1022-1033, 2017.