Plane Thermoelastic Waves in Infinite Half-Space Caused FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 35, No 1, March 2022, pp. 93-106 https://doi.org/10.2298/FUEE2201093S © 2022 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND Original scientific paper A NON-ISOLATED HIGH STEP-UP CONVERTER WITH LOW RIPPLE INPUT CURRENT AND REDUCED VOLTAGE STRESS Asghar Salehi, Mohammad Hossein Ershadi, Mehdi Baharizadeh Department of Electrical Engineering, Khomeinishahr Branch, Islamic Azad University, Khomeinishahr/Isfahan, Iran Abstract. In this paper a new non-isolated high step-up interleaved cascade converter is presented. In comparison with the conventional cascade boost converter, the proposed converter has a higher voltage gain, lower input current ripple and reduced voltage stress for the switches and diodes. Besides, unlike the conventional cascade boost converter, in the proposed converter the input current is shared between inductors and hence the converter can be implemented with lower current rated inductors. Thus, the converter size and conduction losses are reduced and the efficiency is increased. The proposed converter is analyzed and experimental results of a 200W laboratory prototype are presented. Key words: DC-DC converters, soft switching, high step up, voltage stress. 1. INTRODUCTION Nowadays, DC microgrid systems due to their self-sustainability in small areas have been receiving attention and are expected to be the next generation of power systems. Renewable energy sources, such as wind and solar, are increasingly being integrated into the electric power grid, while the power system becomes more tightly intertwined with other systems, such as buildings, natural gas pipelines, and the transportation sector. In microgrid systems, renewable energy sources including photovoltaic (PV), wind turbine, waves, and geothermal sources are utilized for generating DC power and batteries, ultra- capacitors, and fuel cells are adopted as backup power sources for the renewable energy sources [1]-[3]. However, since these power sources usually generate a low voltage, a high step-up DC–DC converter is required to supply high operating voltages loads [4]. For step-up applications, a conventional boost converter can be applied due to its simple circuit and low cost. However, it is not suitable for high step-up applications due to high duty cycle for the converter switch, high voltage stress of the power devices, reverse recovery problems, high conduction losses, stability problems in control and efficiency limitation [5]-[8]. Received May 20, 2021; received in revised form August 27, 2021 Corresponding author: Mohammad Hossein Ershadi Department of Electrical Engineering, Khomeinishahr Branch, Islamic Azad University, Khomeinishahr/Isfahan, Iran E-mail: ershadi@iaukhsh.ac.ir 94 A. SALEHI, M. H. ERSHADI, M. BAHARIZADEH To reach a high voltage gain, two or more boost converters can be connected in series. These converters are called cascade converters [9]. To reduce the number of required components, quadratic boost converters are proposed in [10]-[12]. In these converters, the two series boost converters are integrated and the converter needs only one switch. However, since the input voltage is low and all the input current flows from the first stage inductor, the size, volume and conduction losses of this inductor increase drastically as the output power increases. To solve this problem, interleaved technique can be used in order to share current between modules [13]. However, the voltage gain of two stage cascade boost converter is still limited and more than two stage cascade boost converters suffer from low efficiency, complex circuit and control, and high cost [10]. In recent years various interleaved high step up converters are presented in which the input current of the converter is shared between the interleaved phases. In [14] and [15], switched capacitor technique is applied to the interleaved boost converter and the voltage gain has increased. Although in these converters the voltage gain is higher than conventional boost converter, it is still limited and the voltage stress of semiconductor devices are high. In [16]- [19], coupled inductors are used instead of main inductors in interleaved boost converter and the turn ratio of the coupled inductors is employed to adjust the voltage gain. However, because a high turn ratio is required to obtain a high voltage gain higher than 15, the size of the coupled inductor and the conduction loss of the winding and the core loss increase. Moreover, a snubber circuit or clamping circuit is needed due to the leakage inductance from the coupled inductor [19]-[23]. Besides, in [18] the input current of the converter is pulsating and its ripple is high. To decrease the input current ripple, three coupled inductors are adopted in [20] and [21] which increase the converter size and complexity. To solve the problems of conventional cascade boost converter and avoid using coupled inductors, in this paper a new non-isolated high step-up interleaved cascade converter is presented. The proposed converter has a higher voltage gain in comparison to the two stage cascade boost converter and interleaved boost converter. Moreover, the voltage stress of the switches in the proposed converter is reduced and the input current is shared between converter inductors. Besides, the input current ripple in the converter has decreased compared to the conventional cascade boost converter. Hence, the converter can be implemented with lower current rated inductors, and the converter size and conduction losses are reduced and efficiency is increased. The rest of the paper is organized as follows. The proposed converter operation principals are described in Section II. In section III, converter analysis and design considerations are discussed in details. Experimental results of a prototype converter are presented in Section IV and conclusions are given in Section VI. 2. PROPOSED CONVERTER OPERATION PRINCIPLE Fig. 1 shows the proposed interleaved high step-up converter. In order to indicate the operation of the proposed converter, some assumptions are made: 1) All semiconductor components are ideal; 2) The output capacitor CO and capacitors C1~C3 are large enough and can be considered as voltage sources; 3) The inductors L1, L2 and L3 are large enough and the converter operates in continuous- current-mode (CCM); A Non-Isolated High Step-Up Converter with Low Ripple Input Current and Reduced Voltage Stress 95 L1 L2 S1 S2 S3 D1 C1 D2C2 D3C3 Co R + Vo -D4 L3 Vin IL1 IL2 IL3ID1 ID3 ID2 ID4 IS3 IS1 IS2 + VC1 - - VC2 + - VC3 +- VD1 + - VD2 + - VD3 + - VD4 + IC3 IC2 IC1 + VL2 - + VL3 - + VL1 - + VS1 - + VS3 - + VS2 - IoIin Fig. 1 Proposed interleaved high-step up converter. With respect to above assumptions, each switching period can be divided into four modes and the key operating waveforms of the proposed converter and equivalent circuits are shown in Fig. 2 and Fig. 3, respectively. Likewise, the two-phase interleaved converters, switches S2 and S3are driven with the phase shift angle of 180ºand duty cycles of them are equal. The gate pulse of switch S1 is similar to S2 as it is shown in Fig. 2. Interval I, [t0-t1]: Fig. 3(a) shows the equivalent circuit of the converter in this interval and as it is shown in the figure, switches S1 and S2 are turned off and S3 is turned on. In this interval inductors L1 and L2 are discharged through pathsVin-D1-C1-L1 and Vin-L2-C2- D2-C3-S3, respectively. In addition, inductor L3 is charged through Vin-D1- S3-L3. The equations of converter elements in this interval are as follows: )()()( 0 1 1 011 tt L VV tItI inC LL − − −= (1) )()()()( 0 2 23 0222 tt L VVV tItItI CinC LDL − −− −== (2) )()()( 030 3 3 tItt L V tI L in L +−= (3) )()()( 311 tItItI LLD += (4) )()()( 323 tItItI LLS += (5) Interval II, [t1-t2]: This interval begins when switches S1 and S2 turn on. As it is shown in Fig. 3(b), in this interval all of the switches are turned on and inductors L1, L2 and L3 are charged through Vin-S1-L1, Vin-S1-C1-L3-S3 and Vin-L2-S2, respectively. Important equations of converter elements are as follows: 96 A. SALEHI, M. H. ERSHADI, M. BAHARIZADEH VGS1&VGS2 VGS3 IS1 VS1 IS2 VS2 IS3 VS3 ID1 ID2 ID3&ID4 Iin t0 t1 t3 t4t2 Fig. 2 Typical key waveforms of the proposed converter. )()()( 1 1 111 tt L V tItI in LL −+= (6) )()()()( 1 2 1222 tt L V tItItI in LSL −+== (7) A Non-Isolated High Step-Up Converter with Low Ripple Input Current and Reduced Voltage Stress 97 )()()( 1 3 1 133 tt L VV tItI Cin LL − + += (8) )()()( 311 tItItI LLS += (9) Interval III, [t2-t3]: At t2, S3 turns off and this interval begins. When S3 turns off, L3 continues its current and turns D3 and D4 on. Part of L3 current flows through Vin-S1-C1- L3-C3-D3-Co and the other part of L3 current runs through Vin-S1-C1-L3-D4-C2-S2. Hence, C1 and C3 are discharged and Co and C2 are charged in this interval. L1 and L2 are charged similar to the pervious interval. Important equations of the converter elements are: )()()( 2 1 211 tt L V tItI in LL −+= (10) )()()( 2 2 222 tt L V tItI in LL −+= (11) )()()( 2 3 31 233 tt L VVVV tItI CCino LL − −−− −= (12) )()()( 311 tItItI LLS += (13) Interval IV, [t3-t4]: Fig. 3(b) shows the equivalent circuit of the converter in this interval. The converter operation and its important equations are similar to the second interval. 3. CONVERTER ANALYSIS AND DESIGN CONSIDERATIONS 3.1. Voltage Conversion Ratio Following equations can be obtained from Volt-Second-Balance of L1, L2 and L3, respectively. TDVVDTV inCin )1)(( 1 −−= (14) TDVVVDTV inCCin )1)(( 23 −−−= (15) TDVVVTDVTDVV inCCinCin )1)(()1()12)(( 121 −−−=−+−+ (16) From, (14), (15) and (16) following equations are obtained. 1 )1( Cin VDV −= (17) ))(1( 23 CCin VVDV −−= (18) 12 .)1( CCin VDVDV −−= (19) From (17), (18) and (19), VC1, VC2 and VC3 can be obtained as, )1( 1 D V V in C − = (20) 98 A. SALEHI, M. H. ERSHADI, M. BAHARIZADEH L1 L2 S1 S2 S3 D1 C1 D2C2 D3C3 Co R + Vo -D4 L3 Vin + VC1 - - VC2 + - VC3 + (a) L1 L2 S1 S2 S3 D1 C1 D2C2 D3C3 Co R + Vo -D4 L3 Vin + VC1 - - VC2 + - VC3 + (b), (d) L1 L2 S1 S2 S3 D1 C1 D2C2 D3C3 Co R + Vo -D4 L3 Vin + VC1 - - VC2 + - VC3 + (c) Fig. 3. Equivalent circuits of the proposed converterČ (a) Interval I [t0-t1], (b) Interval II [t1-t2], (c) Interval III [t2-t3] (d) Interval IV [t3-t4]. 22 )1( D V V in C − = (21) 23 )1( ).2( D VD V in C − − = (22) A Non-Isolated High Step-Up Converter with Low Ripple Input Current and Reduced Voltage Stress 99 From Interval III, 32 CoC VVV −= (23) By substituting VC2 and VC3 from (21) and (22) in (23), the voltage gain G of the proposed converter can be obtained as follows: 2 )1( 3 D D V V G in o − − == (24) Relation (24) shows that the proposed converter has a high step up voltage gain. Fig. 4 shows a comparison between the voltage gains of the proposed converter, the conventional cascade boost converter and the converters presented in [14] and [15]. As it can be observed from the figure, the proposed converter has a higher voltage gain. Fig. 4. Voltage gain comparison of the proposed converter with conventional cascade boost converter and the converters presented in [14] and [15]. 3.2. Inductors average current In the proposed converter, input current is sum of the L1, L2 and L3 currents. Hence, the average value of input current is as follows: av gLav gLav gLav gin IIII _3_2_1_ ++= (25) From the current-second-balance of C3 and Co, following equation can be obtained TDITD I avgL avgL )1()1( 2 _3 _2 −=− (26) TITDI av goav gL __3 )1( =− (27) From (26) and (27), av gLav gL II _3_2 2= (28) )1( _ _3 D I I av go av gL − = (29) 100 A. SALEHI, M. H. ERSHADI, M. BAHARIZADEH The following equation can be obtained by assuming ideal condition: oavgooinavgLavgLavgLinavginin VIPVIIIVIP __3_2_1_ )( ==++== (30) So, avgo in o avgLavgLavgL I V V III __3_2_1 )( =++ (31) By substituting IL2_avg,IL3_avgand Vo/Vin from (28), (29) and (24) into (31), average current of inductors are: av gin av go av gL I D D D DI I _2 _ _1 3 2 )1( 2 − = − = (32) avgin avgo avgL I D D D I I _ _ _2 3 )1(2 1 2 − − = − = (33) avgin avgo avgL I D D D I I _ _ _3 3 )1( 1 − − = − = (34) The proposed converter is compared with the conventional cascade boost and converters presented in [14] and [15] in Table 1. From this table, it is obvious that in the proposed converter, unlike the conventional cascade boost converter, the input current is shared between all the inductors. 4. SEMICONDUCTOR STRESS ANALYSIS Based on the converter operating intervals and equivalent circuits, the voltage stress of S1, S2 and D1 is: o in DSS V D D D V VVV . )3( )1( )1( 121 − − = − === (35) Also, the voltage stresses of S3, D3, D2 and D4 are as follows: )3()1( 233 D V D V VV oin DS − = − == (36) )3( ).2( )1( ).2( 242 D VD D VD VV oin DD − − = − − == (37) The voltage stress of the semiconductor components in the proposed converter are compared with some other transformer-less high step up converters in Table 1 and as it can be seen, in the proposed converter the voltage stresses of the components are reduced. When S1 is on, the currents of L1 and L2 flow through this switch and when it turns off its current passes through D1, hence the current stresses of S1 and D1 can be obtained as: ) )( ( 2 1 ) ).1)(( ( 2 1 2 1 1 1 _2_111 L DTVV L TDVV IIII CinCin avgLav gLDS + + −− ++== (38) A Non-Isolated High Step-Up Converter with Low Ripple Input Current and Reduced Voltage Stress 101 The current stresses of other switches and diodes are as follows: ) )( ( 2 1 ) )1)(( ( 2 1 2 1 3 32 _2_32 L DTVV L TDVVV III CinCCin av gLav gLS + + −−+ ++= (39) )] )1)(( ( 2 1 [ 2 1 )( 2 1 2 21 _2 3 _33 L TDVVV I L DTV II CCin av gL in avgLS −−+ +++= (40) )( 2 1 3 _32 L DTV II in avgLD += (41) )] )( ( 2 1 [ 2 1 2 1 _243 L DTVV III Cin avgLDD + +== (42) Table 1 Comparison of the proposed converter with the conventional cascade boost converter and converters presented in [14] and [15]. Proposed Converter Converter presented in [15] Converter presented in [14] Conventional Cascade boost converter Items Voltage Gain )in/Vo(V Voltage Stress of Switches Voltage Stress of Diodes Inductors average current 102 A. SALEHI, M. H. ERSHADI, M. BAHARIZADEH 5. INPUT CURRENT RIPPLE AND INDUCTORS From equations (6), (7) and (8), the input current ripple is obtained as follows: 3 21 21 2 )( 22 L DTVVV L DTV L DTV I CCininin in −+ ++= (43) By replacing VC1 and VC2 from (20) and (21) in (43): 3 2 21 2 ) )1( 1 1 1 1( 22 L DTV DD L DTV L DTV I in inin in − − − + ++= (44) By assuming L = L1 = L2, ) 2 ) )1( 1 1 1 1( 1 ( .2 ) )1( 1 1 1 1( 3 2 3 2 L DD L DTV L DTV DD L DTV I in in in in − − − + += − − − + += (45) From (45), if L D D L )1 )1( ( 2 1 23 − − = (46) , the input current ripple of the converter would be zero. In the case that Vin=40Vand Vo=400V, the converter operating duty cycle from (24) is 0.5 and from (46),L3 is LL 2 1 3 = (47) By substituting L3 from (47) and Vin from (24) in (45), the input current ripple of the proposed converter is obtained as: )2 1 1 )1( 1 ( 2 − − − − = DDL DTV I in in (48) The equation of input current ripple in the conventional cascade converter is: L DTV I in in 2 = (49) Comparing (48) with (49) shows that the proposed converter has a lower input current ripple in comparison to conventional cascade boost converter. The proposed converter operates under continuous current mode (CCM) and the design equation of L1, L2 and can be obtained from (30) and (31) as: )3(4 )1( m in_ 4 21 D TRD LL o − − == (50) 123 )1 )1( ( 2 1 L D D L − − = (51) A Non-Isolated High Step-Up Converter with Low Ripple Input Current and Reduced Voltage Stress 103 6.CAPACITORS The values of the proposed converter capacitors can be obtained from following equations: 1 _ 1 )1( 2 C av go VD DTI C − = (52) 2 _ 2 2 C av go V TI C  = (53) 3 _ 3 2 C av go V TI C  = (54) o av go o V TI C  = 2 _ (55) Where, ΔVC1, ΔVC2, ΔVC2 and ΔVCo are the voltage ripple of C1, C2, C3 and Co, respectively. 7. EXPERIMENTAL RESULTS In order to verify the performance of the proposed converter and the presented key waveforms, a 200 W laboratory prototype is implemented. The component specifications of the proposed converter are summarized in Table2.In order to show the ability of providing high voltage gain, input voltage and output voltages are selected 40V and 400 V, respectively. The switching frequency and duty ratio of the gate signals of all switches are 100 kHz and approximately 0.5, respectively. The experimental waveforms of the converter are shown in Fig. 5. In Fig. 5(a), (b) and (c) the current and voltage waveforms of S1, S2 and S3 are represented, respectively. As shown in the figures, the maximum voltage across S1, S2 and S3for 40V input and 400V output are about 80V, 80V and 160V, respectively. As a result, low voltage rated switches can be adopted to reduce the conduction loss and to achieve high efficiency. In Fig. 5(d), (e), (g) and (h) the current and voltage of D1, D2, D3 and D4are illustrated, respectively. The voltage stress of D1, D2, D3 and D4for 400V output voltage is about 80V, 250V, 160V and 250V, respectively. As can be seen, the voltage stresses of diodes are sufficiently lower than the output voltage. Fig. 6 shows the measured efficiency of the proposed converter compared with the conventional cascade converter. For a fair comparison, the conventional cascade boost converter is designed with the same switching frequency. Other important parameter of the conventional cascade boost converter is mentioned in Table 2. As it can be observed form Fig. 6, the proposed converter has higher efficiency and as the load increases, efficiency drop in the conventional converter is higher compared with the proposed converter. Fig. 7 shows the input and output voltages of the converter. 104 A. SALEHI, M. H. ERSHADI, M. BAHARIZADEH VS1[50V/div] IS1[5A/div] 2.5µS 2.5µSIS3[5A/div] VS3[100V/div] VD1[50V/div] ID1[2A/div] 2.5µS2.5µSIS2[1A/div] VS2[50V/div] (a) (b) VS1[50V/div] IS1[5A/div] 2.5µS 2.5µSIS3[5A/div] VS3[100V/div] VD1[50V/div] ID1[2A/div] 2.5µS2.5µSIS2[1A/div] VS2[50V/div] (c) (d) 2.5µS ID2[2A/div] VD2[100V/div] 2.5µS ID3[2A/div] VD3[50V/div] 2.5µS ID4[2A/div] VD4[50V/div] (e) (f) (g) Fig. 5. Experimental voltage and current waveforms of the proposed converter semiconductor components (a) S1, (b) S2, (c) S3, (d) D1, (e) D2, (f) D3 and (g) D4. Fig. 6 Measured efficiency of the proposed converter. A Non-Isolated High Step-Up Converter with Low Ripple Input Current and Reduced Voltage Stress 105 Table 2 Components value and specification of the implemented converters Parameter Value Proposed Converter Conventional Cascade Converter Switching frequency 100 kHz 100 kHz Switches S1~S3 (IRF640) S1 (IRFP260) S2(IRFP460) Diodes D1~D4 (MUR460) D1 (BYV32-200) D2 (MUR460) Inductors L1 and L2 (500 µH) L3(250 µH) L1 (1mH) L2(500 µH) Capacitors C1 (10µF/ 100V) C2 (10µF/ 200V) C3 (10µF/ 450V) Co(47µF/ 450V) C1 (22µF/ 200V) Co(100µF/ 450V) Vo 100V Vin 50V 2.5µs Fig. 7 Input and output voltage waveforms of the sample converter 8.CONCLUSIONS A new interleaved cascade boost DC–DC converter with an improved voltage gain is presented in this paper. In the proposed converter, the input current is continuous with low ripple and the converter does not need additional filter in the input. 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