Plane Thermoelastic Waves in Infinite Half-Space Caused FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 35, No 1, March 2022, pp. 29-41 https://doi.org/10.2298/FUEE2201029B © 2022 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND Original scientific paper ALL-OPTICAL FREQUENCY ENCODED DIBIT-BASED PARITY GENERATOR USING REFLECTIVE SEMICONDUCTOR OPTICAL AMPLIFIER WITH SIMULATIVE VERIFICATION* Surajit Bosu1, Baibaswata Bhattacharjee2 1Department of Physics, Bankura Sammilani College, Bankura, India (W.B) 2Department of Physics, Ramananda College, Bishnupur, Bankura, India (W.B) Abstract. High-speed signal computation and communication are an essential part of modern communication that increases optical necessity. Therefore, researchers developed different types of digital devices in the all-optical domain. Due to the versatile gain medium of reflective semiconductor optical amplifiers (RSOAs), it has various important applications in passive optical networks. In comparison with semiconductor optical amplifier (SOA), RSOAs exhibit better gain performance because of their double pass property. Therefore, RSOA shows better switching properties. In this communication, co-propagation scheme of RSOA is used to design and analyze a frequency encoded dibit-based parity generator. Taking the advantages of RSOA like high switching speed, low noise, high gain, and low power consumption, the proposed design achieves these qualities. This design simulated in MATLAB and simulated outputs accurately verify the truth table. Key words: Optical communication, Reflective semiconductor optical amplifier, Frequency encoding, Dibit-based logic system, Parity generator. 1. INTRODUCTION The photon becomes more popular for information transmission [2, 3]. Photons can carry information at a superfast speed. Therefore, the researchers are very interested to design photon-based devices [4, 5] instead of electron-based devices. The data signal can be transmitted in long-range using different types of encoding techniques [6-8]. The frequency encoding [9-13] technique is more reliable in long-range signal propagation. In optical communication, the adder [1, 14-16], subtractor [17], comparator [9, 18], parity generator are basic components for arithmetic, decision-making circuits, logic units [19- 25], and memory units [11]. Received August 9, 2021; accepted September 29, 2021 Corresponding author: Surajit Bosu Bankura Sammilani College, Faculty of Physics, Bankura, West Bengal, India E-mail: surajitbosu7@gmail.com * An earlier version of this paper was presented at the 4th International conference on 2021 Devices for Integrated Circuit (DevIC 2021), May 19-20, 2021, in Kalyani, West Bengal, India [1]. 30 S. BOSU, B. BHATTACHARJEE These are the basic building blocks of optical data processors. In the frequency encoding concept [1], the digital logic states ‘0’ and ‘1’ are indicated by frequencies υ1 and υ2 respectively. In communication and data storage systems, the parity generator is a very essential device. In the last decade, researchers are working for parity generators. From the literature survey, it is found that the even/odd parity generator units are not designed in a single device and also dibit-based logic and frequency encoding scheme is also first time implementation. In this communication, a frequency encoded dibit-based even/odd parity generator in the all-optical domain, using add/drop multiplexer (ADM) and reflective semiconductor optical amplifier (RSOA) is devised. From the previous version [1], we adopted the logic of SUM from the design of a half adder using RSOA and ADM. In half-adder design [1], two input dibit-based logic is used but in this proposed design, we have implemented three inputs dibit-based logic. So the operation of the three inputs dibit-based logic is much more complicated than the previous version [1]. This proposed design is a single device for the even/odd parity generator units and it has no extra control terminal. As a result, the devised design reduces the space of the device as well as simultaneously generates even and odd parity. Introducing the dibit-based logic in this design, one can be expected a high degree of parallelism. The frequency encoding and dibit-based systems reduce also the bit error problems and enhance the speed of operation in long-range transmission. Since RSOA has ultrafast switching property with low noise, so the proposed design operates at ultrafast speed. In the results and discussion section, the proposed design is compared with the other designs [26, 28, 33, 36] which are given in Table 3. The remaining part is structured as follows: Related works are described in Section 2. The working principle of RSOA and ADM are described in Section 3. Section 4 describes the operation scheme of the proposed parity generator. The simulation experiment of the proposed model is described in Section 5. The results and discussion of the proposed system are presented in Section 6. Finally, the conclusions with potential future works are given in Section 7. 2. RELATED WORKS The researchers are working for parity generators during the past several years. Some of these legendary works are discussed here. Chowdhury et al. [26] have introduced a design of 4-bit parity generator and checker using non-linear material-based switches. Using spatial light modulator and Savart plate a parity generator and parity checker has been reported by Ghosh [27]. Dimitriadou et al. [28] have introduced a 4-bit parity generator and checker. They used a high-speed switch to design the parity generator. This high-speed switch is based on Quantum-Dot-SOA-based MZI and their design is verified through numerical simulation. This design is based on the modified trinary number system. A micro-ring-resonator (MRR)-based parity generator and checker have been reported by Rakshit et al. [29] and it also verified using numerical simulation. Mehra et al. [30] have introduced an SOA-MZI-based 7-bit parity generator and checker circuit. This design is simulated at high-speed 120 GHz. Bhattacharyya et al. [31] have reported a 4-bit parity generator using an SOA-assisted Sagnac switch and the design is verified through numerical simulation. Kumar et al. [32] have reported a parity checker using the electro-optic effect in MZI. Using the MATLAB software, results are obtained and Frequency Encoded Dibit-Based Parity Generator 31 optiBPM software is used for verification of the implementation of this design. Wang et al. [33] have reported parity checker in the all-optical domain and the works implemented in the nanoscale-integrated chip. Plasmonic Metal-Insulator-Metal (MIM)-based parity generator has been reported by Singh et al. [34]. This design is simulated in MATLAB. Kaur et al. [35] have proposed an SOA-MZI-based 3-bit parity generator and checker and also transfer matrix method (TMM) based time-domain simulation is done for this design. Nair et al [36] have introduced an SOA-MZI-based 3-bit parity generator and checker in the all-optical domain. They used the tree architecture concept to design their work. Maji et al. [37] have proposed a design of a 4-bit parity generator and checker using a reflective semiconductor optical amplifier. They have introduced a single device in which even/odd parity generator units are designed but they have used an extra control terminal to switch between the even-odd parity units. 3. WORKING PRINCIPLE OF RSOA AND ADM As mentioned in the introduction, the basic key components of the proposed design are RSOA and ADM. Now, the working principle of these two is logically explained in this section. So, one pump signal (strong) and a probe signal (weak) are injected into the input signals of SOA but a high power probe beam is obtained at the output. This design is based on cross gain modulation (XGM) [1, 38]. Therefore, it is called RSOA. A high reflective (HR) and an anti-reflective (AR) coating are placed in the two facets of RSOA [1, 22, 25, 38-41]. It has a very versatile high gain medium so it has various important applications in passive optical networks (PON). Here, the frequency corresponding to the wavelengths of the probe signals is in the C-band (1535-1570 nm). The saturation power of RSOA may be used within 5-20 dBm [1, 9, 43]. Fig. 1 Block diagram of RSOA An add/drop multiplexer (ADM) [41-43] is very popular as a frequency selector. If we consider, the frequencies, υ2 and υ1 are injected into the bias and input port of ADM respectively, then at the output frequency, υ1 is obtained whereas nothing at the drop port. If we consider the same frequency, υ1 (or υ2) into the input and bias port then ADM reflects the input signal, υ1 (or υ2) at the drop port by the circulator whereas nothing is obtained at the output. The schematic diagram of ADM is given in Fig. 2. RSOA and ADM are used to develop different devices such as multiplexer, adder, comparator, etc. [1, 9-10, 41]. 32 S. BOSU, B. BHATTACHARJEE Fig. 2 Block diagram of ADM 4. PROPOSED SCHEME OF OPERATION OF THE THREE-BIT PARITY GENERATOR In this section, the 3-bit parity generator and its operational scheme is proposed. Here, A, B, and C are the frequency encoded dibit-based inputs whose parity will be generated. The Boolean expression of even and odd parity generators are even Y A B C=   (1) oddY A B C=   (2) The schematic diagram of this design is given in Fig. 3. In this proposed design, frequency encoding technique and dibit-based logic are opted. Mukhopadhyay [44] first reported the dibit-based representation technique. According to this representation technique [1, 9-10, 42-44], two consecutive bit positions are chosen to represent a digit. Here, digital logic states ‘0’ and ‘1’ are represented by the dibits ‘01’ and ‘10’ respectively. Since the proposed design is frequency encoding, so two different frequencies υ1, and υ2 when placed side by side as ‘‘υ2 υ1’’ indicates the logic state ‘1’ and ‘‘υ1 υ2’’ indicates the digital logic state ‘0’. Here, we adopted the logic of SUM from the design of half adder [1] using RSOA and ADM. In half-adder design, two inputs dibit-based logic are used but in this proposed design, we have implemented three inputs dibit-based logic. So the operation of the three inputs dibit-based logic is much more complicated than the previous version [1]. The operation of the proposed designs is based on the Eqs. 1-2. Now, the operation scheme of the proposed frequency encoded dibit-based parity generator describe in the following cases. 4.1. Case-I (When all the inputs are the same) In this case, A/=υ1, A //=υ2, B /=υ1, B //=υ2, C /=υ1, C //=υ2 frequencies are injected into the input terminals. Therefore, υ1 frequencies are obtained from the RSOA-3, RSOA-2, and RSOA-1. The outputs of RSOA-2 and RSOA-1 are injected into A4 (ADM-4) as input and bias signals. Since both the frequency, of A4 is the same then frequency, υ1 is obtained at the drop port through the circular. This frequency, υ1 acts as a pump signal of RSOA-5 and probe signal frequency, υ1 so the output of RSOA-5 is frequency, υ1. This frequency, υ1 acts as an input signal of A5 (ADM-5) and its biasing signal is υ1 which is the output frequency of RSOA-3. Since both the frequencies of A5 (ADM-5) are the Frequency Encoded Dibit-Based Parity Generator 33 same then A5 reflects the input signal, υ1 at the drop port. This frequency, υ1 works as a pump signal of RSOA-7. Therefore, the output of RSOA-7 is frequency, υ1. One part of this frequency directly shows the dibit output Y/even and another part acts as an input of A6 (ADM-6) which is biased by the signal of frequency, υ2. Therefore, A6 selects the input signal of frequency, υ1 to the output and this output frequency, υ1 works as the pump signal of RSOA-8. This yields υ2 at the dibit output terminal, Y // even. Finally, the dibit outputs υ1 and υ2 are obtained at the output terminals, Y / even and Y//even respectively, which indicates the digital logic state ‘0’ and the dibit outputs υ2, υ1 are obtained at the dibit output terminals, Y/odd and Y//odd which altogether indicates the digital logic state ‘1’. Therefore, when inputs, A=0, B=0, and C=0 then the outputs show even parity, Yeven=0 and odd parity, Yodd =1. Similarly, when A/=υ2, A //=υ1, B /=υ2, B //=υ1, C /=υ2, and C //=υ1 are taken as input signals to the device then the dibit outputs υ1, υ2 are obtained at the dibit output terminals, Y/even and Y//even respectively which altogether indicates the digital logic state ‘0’ and the dibit outputs υ2, υ1 are obtained at the dibit output terminals, Y / odd and Y//odd which altogether indicates the digital logic state ‘1’. Therefore, when inputs, A=1, B=1, and C=1 then the outputs show even parity, Yeven=0 and odd parity, Yodd =1. 4.2. Case-I I (When one input is different) Here, A/=υ2, A //=υ1, B /=υ1, B //=υ2, C /=υ2, and C //=υ1 are applied as the input signals of the device. Therefore, frequencies, υ2, υ1, and υ2 are obtained at the outputs of RSOA-3, RSOA-2, and RSOA-1 respectively. The outputs from RSOA-2 and RSOA-1 are injected into the A4 (ADM-4) as input and biasing signals respectively. Since both the frequencies of A4 are not the same then the input signal is selected by the A4 at the output. This frequency, υ1 acts as a pump signal of RSOA-4 and its probe signal is υ2 so the output of RSOA-5 is υ2. This frequency, υ2 acts as an input frequency of A5 (ADM-5), and the output frequency, υ2 of RSOA-3 works as biasing frequency. Since both the frequency of A5 (ADM-5) are the same then A5 reflects the input signal of frequency, υ2 at the drop port. This frequency, υ2 works as a pump signal of RSOA-7. Therefore, the output of RSOA-7 is frequency, υ1, one part of this frequency directly shows the dibit output Y / even and another part acts as an input of A6 (ADM-6) which is biased with the frequency, υ2. Therefore, A6 selects the frequency, υ1 at the output, and this output frequency, υ1 acts as pump signal of RSOA-8 which gives υ2 at the dibit output terminal, Y // even. Finally, the dibit output υ1 and υ2 are obtained at the output terminals, Y / even and Y//even respectively, which indicates the digital logic state ‘0’ and the dibit outputs υ2 and υ1 are obtained at the dibit output terminals, Y/odd and Y//odd which altogether indicates the digital logic state ‘1’. Therefore, when inputs, A=1, B=0, and C=1 then the outputs show even parity, Yeven=0 and odd parity, Yodd =1. 34 S. BOSU, B. BHATTACHARJEE Fig. 3 Schematic diagram of proposed parity generator Frequency Encoded Dibit-Based Parity Generator 35 Similarly, when A/=υ1, A //=υ2, B /=υ2, B //=υ1, C /=υ2, and C //=υ1 are taken as input signals to the device then the dibit outputs υ1, υ2 are obtained at the dibit output terminals, Y/even and Y//even respectively which altogether indicates the digital logic state ‘0’ and the dibit outputs υ2, υ1 are obtained at the dibit output terminals, Y / odd and Y//odd which altogether indicates the digital logic state ‘1’. Therefore, when inputs, A=0, B=1, and C=1 then the outputs show even parity, Yeven=0 and odd parity, Yodd =1. In this way, other outputs can be obtained and these are given in Table 1. Table 1 Frequency encoded truth table of proposed design Dibit Input Dibit Output Input (A) Input (B) Input (C) Even parity (Yeven) Odd parity (Yodd) A/ A// B/ B// C/ C// Y/even Y // even Y / odd Y // odd υ1 υ2 υ1 υ2 υ1 υ2 υ1 υ2 υ2 υ1 υ1 υ2 υ1 υ2 υ2 υ1 υ2 υ1 υ1 υ2 υ1 υ2 υ2 υ1 υ1 υ2 υ2 υ1 υ1 υ2 υ1 υ2 υ2 υ1 υ2 υ1 υ1 υ2 υ2 υ1 υ2 υ1 υ1 υ2 υ1 υ2 υ2 υ1 υ1 υ2 υ2 υ1 υ1 υ2 υ2 υ1 υ1 υ2 υ2 υ1 υ2 υ1 υ2 υ1 υ1 υ2 υ1 υ2 υ2 υ1 υ2 υ1 υ2 υ1 υ2 υ1 υ2 υ1 υ1 υ2 5. SIMULATION OF THE PROPOSED PARITY GENERATOR In the previous section, the operational scheme of the proposed design is explained theoretically. Now, we discuss the simulation model of the proposed design. Using MATLAB (R2018a) software, the proposed design of the parity generator is verified. RSOAs and ADMs are programming on the basis of their characteristics using MATLAB language. If frequencies, υ1=193.5 THz (wavelength=1550 nm) and υ2=194.1 THz (wavelength=1545 nm) are considered as the probe signal and pump signal then, 193.5 THz is obtained at the output port whereas 194.1 THz is obtained at the output port when υ1=193.5 THz (wavelength=1550 nm) and υ2=194.1 THz (wavelength=1545 nm) are considered as the pump and probe signals. If frequencies, υ1=193.5 THz and υ2=194.1 THz are considered as the input and biasing signals then, ADM selects the input signal (193.5 THz) at the output whereas nothing is obtained at the drop port. If the same frequencies are injected at the biasing and input port then, ADM reflects the input signal at the drop port whereas output gives nothing. By the use of these considerations, this design is simulated. In Figs. 4, and 5, dibits <193.5><194.1> and <194.1><193.5> indicate the digital logic states ‘0’, and ‘1’ respectively. From Fig. 4, the dibits <193.5><194.1>, <194.1><193.5> and <193.5><194.1> are injected into the dibit inputs ‘A’, ‘B’ and ‘C’ terminals of the device respectively. As a result, <194.1><193.5> and <193.5> <194.1> are obtained as dibit even parity, Yeven and dibit odd parity, Yodd at the output terminals respectively. Dibits <194.1><193.5>, <194.1><193.5>, and <193.5><194.1> are injected into the dibit inputs ‘A’, ‘B’, and ‘C’ terminals respectively. As a result, <193.5><194.1> and <194.1><193.5> are obtained as dibit even parity, Yeven and dibit odd parity, Yodd at the output terminals 36 S. BOSU, B. BHATTACHARJEE respectively. <194.1><193.5>, <194.1><193.5>, and <194.1><193.5> are injected into the dibit inputs ‘A’, ‘B’ and ‘C’ terminals respectively. Therefore, <194.1><193.5>, and <193.5><194.1> are yielded as dibit even parity, Yeven and dibit odd parity, Yodd at the output terminals respectively. Similar way, other outputs are obtained corresponding to the applied inputs. All the dibit output waveforms corresponding to the dibit input waveforms are given in Fig. 5. The results of the simulation are discussed in the next section. Fig. 4 Dibit input signal waveforms of parity generator Frequency Encoded Dibit-Based Parity Generator 37 6. RESULTS AND DISCUSSION In this section, the theoretical interpretation and the simulation results are discussed. In this design, two signals with different frequencies, υ1=193.5 THz and υ2=194.1 THz are injected into the 50 ps time intervals to the input. The input and output signal waveforms are given in Figs. 4 and 5. The simulation (given in Table 2) verifies the parity generator results. Fig. 5 Dibit output signal waveforms of parity generator 38 S. BOSU, B. BHATTACHARJEE In the first 50 ps, we applied “υ1 υ2” in A, “υ1 υ2” in B, and “υ1 υ2” in C that indicates A=0, B=0, and C=0. After simulation with these data, we obtained Y/even=υ1, Y // even=υ2, and Y/odd=υ2, Y // odd=υ1 that indicates Yeven=0, and Yodd=1. In 50-100 ps, we applied “υ1 υ2” in A, “υ1 υ2” in B, and “υ2 υ1” in C that indicates A=0, B=0, and C=1. After simulation with these data, we obtained Y/even=υ2, Y // even=υ1, and Y / odd=υ1, Y // odd=υ2 that indicates Yeven=1, and Yodd=0. In 100-150 ps, we applied “υ1 υ2” in A, “υ2 υ1” in B, and “υ1 υ2” in C that indicates A=0, B=1, and C=0. After simulation with these data, we obtained Y/even=υ2, Y // even=υ1, and Y / odd=υ1, Y // odd=υ2 that indicate Yeven=1, and Yodd=0. In 150-200 ps, we applied “υ1 υ2” in A, “υ2 υ1” in B, and “υ2 υ1” in C that indicates A=0, B=1, and C=1. After simulation with these data, we obtained Y/even=υ1, Y // even=υ2, and Y/odd=υ2, Y // odd=υ1 that indicate Yeven=0, and Yodd=1. In 200-250 ps, we applied “υ2 υ1” in A, “υ1 υ2” in B, and “υ1 υ2” in C that indicates A=1, B=0, and C=0. After simulation with these data, we obtained Y/even=υ2, Y // even=υ1, and Y / odd=υ1, Y // odd=υ2 that indicate Yeven=1, and Yodd=0. In 250-300 ps, we applied “υ2 υ1” in A, “υ1 υ2” in B, and “υ2 υ1” in C that indicates A=1, B=0, and C=1. After simulation with these data, we obtained Y/even=υ1, Y//even=υ2, and Y / odd=υ2, Y // odd=υ1 that indicates Yeven=0, and Yodd=1. In 300-350 ps, we applied “υ2 υ1” in A, “υ2 υ1” in B, and “υ1 υ2” in C that indicates A=1, B=1, and C=0. After simulation with these data, we obtained Y/even=υ1, Y // even=υ2, and Y / odd=υ2, Y // odd=υ1 that indicates Yeven=0, and Yodd=1. In 350-400 ps, we applied “υ2 υ1” in A, “υ2 υ1” in B, and “υ2 υ1” in C that indicates A=1, B=1, and C=1. After simulation with these data, we obtained Y/even=υ2, Y // even=υ1, and Y / odd=υ1, Y // odd=υ2 that indicate Yeven=1, and Yodd=0. After the verification of the simulation results (given in Table 2), and the truth table (Table1), it is interpreted that the proposed design works accurately. A comparative study with previous work is given in Table 3. Table 2 Simulation results of proposed parity generator (all the frequencies are in THz range) Dibit Input Dibit Output Time (ps) Input (A) Input (B) Input (C) Even parity (Yeven) Odd parity (Yodd) A/ A// B/ B// C/ C// Y/even Y // even Y / odd Y // odd 0-50 193.5 194.1 193.5 194.1 193.5 194.1 193.5 194.1 194.1 193.5 51-100 193.5 194.1 193.5 194.1 194.1 193.5 194.1 193.5 193.5 194.1 101-150 193.5 194.1 194.1 193.5 193.5 194.1 194.1 193.5 193.5 194.1 151-200 193.5 194.1 194.1 193.5 194.1 193.5 193.5 194.1 194.1 193.5 201-250 194.1 193.5 193.5 194.1 193.5 194.1 194.1 193.5 193.5 194.1 251-300 194.1 193.5 193.5 194.1 193.5 194.1 193.5 194.1 194.1 193.5 301-350 194.1 193.5 194.1 193.5 193.5 194.1 193.5 194.1 194.1 193.5 351-400 194.1 193.5 194.1 193.5 194.1 193.5 194.1 193.5 193.5 194.1 Frequency Encoded Dibit-Based Parity Generator 39 Table 3 Comparative Study with previous work Work Simulation of bit pattern given RSOA used or not Even and Odd parity generator in one device Without Extra Control Signal Dibit logic used or not Ref. [26] No No No No No Ref. [28] Yes No No No No Ref. [33] Yes No No No No Ref. [37] Yes Yes Yes No No Proposed Work Yes Yes Yes Yes Yes 7. CONCLUSIONS In this communication, RSOA and ADM are utilized to design a frequency encoded dibit-based 3-bit parity generator. In this devised design, input dibit control units pass the error-free dibit logic that decreases the bit-error problems and enhances the operational speed. So, it promotes reliable and faithful operation. MATLAB software is used to simulate and verify the devised design. Furthermore, a comparative study with parity generators designed using different nonlinear materials has been conducted. This design is a single device for the even/odd parity generator units and it has no extra control terminal. As a result, the devised design reduces the space of the device as well as simultaneously generates even and odd parity. By introducing the dibit-based logic in this design, a high degree of parallelism can be expected. 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