id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
fuelectenerg-6813	Pal, Jayanta; Bhowmik, Dhrubajyoti; Singh, Ayush Ranjan; Saha, Apu Kumar; Sen, Bibhash	SYNTHESIS OF COMPOSITE LOGIC GATE IN QCA EMBEDDING UNDERLYING REGULAR CLOCKING	2021	17	.pdf	application/pdf	6979	482	64	QCA Clocking Apart from the basic building blocks in QCA design, it is also essential to have an appropriate synchronization of clock signals with the majority gate with optimization in delay. The graph representing the total power dissipation can also be noticed that the use of regular clocking in QCA design may lead to higher power dissipation.	cache/fuelectenerg-6813.pdf	txt/fuelectenerg-6813.txt