id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
fuelectenerg-7531	Rao, K Srinivasa; Aditya, Marupaka; Raja, B.S.D. Karthik; Manisai, CH.; Tharun Sai Reddy, M; Girija Sravani, K.	DESIGN AND PERFORMANCE ANALYSIS OF FULL ADDER USING 6-T XOR–XNOR CELL	2022	12	.pdf	application/pdf	3828	218	68	The proposed full adder circuit at 90 nm technology is applicable for higher order cascaded full adder circuits and practical applications at lower supply voltages. In [5], a technique is proposed to access the timing behavior of hybrid full adder, made of both CMOS and FinFET technologies of size 32-nm, and compare their performance in multistage circuits in HSPICE tool.	cache/fuelectenerg-7531.pdf	txt/fuelectenerg-7531.txt