id	author	title	date	pages	extension	mime	words	sentence	flesch	summary	cache	txt
fuelectenerg-980	Balasubramanian, Padmanabhan	A LATENCY OPTIMIZED BIASED IMPLEMENTATION STYLE WEAK-INDICATION SELF-TIMED FULL ADDER	2015	15	.pdf	application/pdf	6847	290	57	Biased implementation Seitz’s weakly indicating full adder design [18], shown in Figure 5, constitutes a good example for the biased implementation style, and synthesizes (1) to (4). Performance comparisons of the proposed full adder vis-à-vis other strong and weak- indication full adders are done on the basis of a 32-bit self-timed ripple carry adder architecture, with the full adders and ripple carry adders realized using a 32/28nm CMOS process.	cache/fuelectenerg-980.pdf	txt/fuelectenerg-980.txt