11834 FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 36, No 4, December 2023, pp. 553 - 565 https://doi.org/10.2298/FUEE2304553D © 2023 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND Original scientific paper IMPACT OF HIGH-K METAL OXIDE AS GATE DIELECTRIC ON THE CERTAIN ELECTRICAL PROPERTIES OF SILICON NANOWIRE FIELD-EFFECT TRANSISTORS: A SIMULATION STUDY Sanat Kr. Das1, Bibek Chettri1, Prasanna Karki1, Bhakta Kunwar2, Pronita Chettri1, Bikash Sharma3 1Department of Physics, Sikkim Manipal Institute of Technology, Majitar, Sikkim, India 2Department of Physics, Nar Bahadur Bhandari Govt. College, Gangtok, Sikkim, India 3Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Majitar, Sikkim, India Abstract. Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-κ HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-κ HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperature- induced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models. Key words: high-κ dielectric, MOSFET, nanowire, metal oxide, transconductance Received May 17, 2023; revised August 10, 2023 and September 29, 2023; accepted November 02, 2023 Corresponding author: Bikash Sharma Sikkim Manipal Institute of Technology, Sikkim, India E-mail: ju.bikash@gmail.com 554 S. K. DAS, B. CHETTRI, P. KARKI, B. KUNWAR, P. CHETTRI, B. SHARMA 1. INTRODUCTION Low-dimensional structures chemically created have recently attracted a lot of interest as precursors for upcoming electronic components like MOSFETs (metal oxide field-effect transistors) [1–5]. Silicon (Si) is now being reconsidered as a potential electronic material for future device miniaturization and enhancement, owing to its superior carrier mobility and drift characteristics in gate dielectrics. SiNWs MOSFET multi-gate device configurations offer enhanced electrostatic control, due to their heightened mobility and current capabilities [6–9]. Extensive work has been carried out on several device topologies, including multi (especially double) gate and all-around gate, to limit Short Channel Effects (SCEs) under a threshold while achieving the core benefits of scaling, such as integrated density, reduced power, and improved performance [2–4]. The Near Ballistic (NB) SiNWs MOSFET with HfO2 as the gate dielectric requires a physics-based analytical model to fully comprehend the operation of the device and to analyse its Current-Voltage and other electrical characteristics [3–7]. For estimating the inversion charge of cylindrical surrounding gate transistors, Roldan et al. combined quantum effects with a semiempirical paradigm and was able to accurately solve the 2D Poisson and Schrodinger equations using a self- consistent simulator. The short channel effects, such as increasing Drain Induced Barrier Lowering (DIBL) and leakage currents, are becoming a very serious problem as a result of the semiconductor industry's rapid increase in downscaling to the nano-regime. Various studies have been conducted over the past years to identify alternative device channels. In order to address the scaling issues of conventional transistors, device structures like Double- Gate (DG), Surrounding-Gate (SG), Cylindrical Gate-All-Around (CGAA), Cylindrical- Surrounding Double-Gate (CSDG), Carbon Nanotube (CNT), Fin-FETs, and Graphene Nanoribbon (GNR) transistors have been developed [7–9]. A pure body cylindrical semiconductor-based nanowire device's potential distribution was modelled physically in 2008 by Ray and Mahapatra. This type worked well with both long and short channel devices. Using the suggested model, it was demonstrated that devices with identical channel lengths exhibit potential drop across gate vs potential drop across body characteristics, but many body radii pass through a crossover point (a single common point) [8–14]. The influence of body radius on the threshold voltage of the double-gate Nano Wire (NW) transistors was examined using this crossover point. The I-V characteristics of a Quasi Ballistic (QB) SiNW MOSFET with high-κ HfO2 as gate dielectrics will be investigated in this work, which is in a remarkable agreement with the modelled and TCAD simulated results [15–21]. Furthermore, we analyzed the transconductance of Natori's Quasi-Ballistic Model (NBM) with Quasi-Ballistic model (QB) SiNW MOSFET devices which is severely declining, as the potential drop across gate voltage increases. In the process of establishing an analytical equation for drain current and showing that the SiNW MOSFET model with high-κ HfO2 exhibits enhanced drain current relative to a QBD, the work establishes a strong agreement between model-generated and TCAD-simulated data and provides insights for device design. Additionally, it emphasises the complex relationship between gate voltage, temperature, mobility, and transconductance, improving our comprehension of SiNW MOSFET behaviour under external influences and having repercussions for cutting-edge semiconductor applications. Impact of High-K Metal Oxide as Gate Dielectric on the Certain Electrical Properties of Silicon … 555 2. QUASI BALLISTIC ANALYTICAL MODELS Fig. 1 depicts the cross-section view of a SiNW MOSFET with discrete random dopants and a HfO2 gate dielectric. The schematic diagram is displayed in Fig. 2 as well. The source and drain of the NWs are made of n-type regions, and the electronic configuration of the NWs is processed using a tight-binding model [21–24]. The intermediate channel area is 15 nm long and contains charged impurities that are dispersed randomly and have a doping concentration of 1018 cm3. Here, the direction of current is along the x-axis and the cross section of the wire is in the y-z plane, as opposed to other designs where the high- κ gate dielectric is 2 nm thick HfO2 [25]. Fig. 1 Cross-sectional view of the SiNWs MOSFET with HfO2 as gate dielectrics with the dimensional parameters [15] Fig. 2 A schematic view of the SiNWs MOSFET with HfO2 as gate dielectrics [25] The 2-D Poisson’s Equation is given by: 2 2 1 ( , z) ( , z) a Si qNr r r r r r r         + =         (1) where (r, z) is the silicon film's electrostatic potential, q is the electronic charge, εSi is the silicon's permittivity, and Na stands for the channel doping concentration. Fundamental parabolic function. 2 0 1 2( , z) ( ) ( ) ( )r S z S z r S z r = + + (2) where S0(z), S1(z), and S2(z) are functions of z only. 556 S. K. DAS, B. CHETTRI, P. KARKI, B. KUNWAR, P. CHETTRI, B. SHARMA The Poisson equation is solved separately using the boundary conditions. The channel surface potential is given by, ( ) ( , )S S Siz r T z = = (3) The surface potential at drain end is, ( , ) ( ) |Si S z L bi dsr T z L z V V  == = = = + (4) Here, we use Natori's quasi-ballistic model to optimize carrier transport utilizing a quantum mechanical technique [7–14] and the Boltzmann transport equation (BTE, direct solution). Our SiNW MOSFET model can have its drain current evaluated using Natori's quasi- ballistic model with drain bias VD. ( , ) ( , ) ( ) D impS impDi i q I f f d    =  −       (5) At source electrode the Fermi distribution function (f ( , μimpS)) is given as 1 ( , ) 1 impS B impS k T f e   −        = + (6) At this point Γi ( ) = transmission coefficient of a carrier injected into the sub band (i=0,1.) whereas f ( , μimpS) and f ( , μimpD) are fermi levels associated with the source and drain. electrodes respectively. And at drain electrode the Fermi distribution function f ( , μimpS) is given as 1 ( , ) 1 impD B impD k T f e   −        = + (7) The preceding equation therefore provides a simplified formula for the difference in fermi energy level. 2 2 1 ( , ) ( , ) 2 impS D impS impS D impS impS impD B B B B qV qV f f k T k T k T k T       − + − + + −       −  = − + −            (8) The above equation is modified as, 1 2 1 1 ( , ) ( , ) 1 1 impS impD x x f f e e   −  = − + + (9) 1 21 1( , ) ( , ) (1 ) (1 ) x x impS impDf f e e  − − −  = + − + (10) Using binomial series expansion we get, 2 1( , ) ( , ) 1 x x impS impDf f e e  −  = − + (11) After further modification for the difference in Fermi energy level between the Source and Drain electrodes, we obtain the condensed expression as follows: Impact of High-K Metal Oxide as Gate Dielectric on the Certain Electrical Properties of Silicon … 557 ( , ) ( , ) 1 impS iD D impS impD B B B B qV qV f f k T k T k T k T        −  = − + +    (12) By a change of variable from x to p ≡ (qE) – 1ln[x + εi / qE] and transformed into simpler form i.e., 0 2 ( ) 0 i dE B F G m Dp + − = (13) and 0 2 ( ) 0 i dG B G F m Dp + − = (14) It is resolved using boundary conditions. Conditions are F0 and G(x0) = Gx0 . In the channel, R is represented as the back injection ratio, B0 is a constant that denotes the intensity of scattering, and D0 is a constant that denotes optical phonon emission. Flux equations that characterize the flux distribution, such as F(x) and G(x), are also used. The flow equation is reduced to a simple form by modifying the variables. We found as 0 0 0 0 0 0 0 ln ln 2 2 ( ) ln 2 i x i i x i x x i i i x i i m qE m qE qE B F B G qE F x m qE qE B                + +    + +            +             =    + +         (15) 0 0 0 0 0 0 0 ln ln 2 2 ( ) ln 2 i x i i x i x x i i i x i i m qE m qE B F qE B G qE G x m qE qE B                + +    + +            +             =    + +         (16) ( ) ( ) * * 0 * 0 0 0 2 1 2 2 ln D qEimpS iD D D ii qV B B B B iD i DqV qVq I d k T k T k T k T B D qE m          − +       = − + +     − +      (17) * * * * * * 2 ln 1 ln D D impSD D D D D ii qV B B B B B i iD qV B B i qV qV qV qVq A I d k T k T k T k T k T B C AqV k T k T B C              −  −   = − + +     +     +   +        (18) By carryout changing the limits and we achieve 558 S. K. DAS, B. CHETTRI, P. KARKI, B. KUNWAR, P. CHETTRI, B. SHARMA * * * * 2 *1 2 1 2 ln 1 ln( ) D D impS iD D D DqV D ii B B B B B i i i iD qV B B i qV qV qV qVq A I d k T k T k T k T k T B C AqV dx k T k T B C x              − −   = − + +      +     + +    (19) The drain current ID value is calculated by replacing the value of the transmission coefficient and the Fermi energy level difference between the source and drain electrodes. * * * * 2 2 1 2 1 2 ln( ) 1 ln( ) D D impS i i iD D D D qV D i B B B B B i i i iD qV B B i AqV qV qV qVq I dx k T k T k T k T k T B C x AqV dx k T k T B C x               − −   = − + +  +  + +    (20) This example gives the electric field at the silicon-oxide interface as, 0 ( )( , ) | ln 1 ox G S r Si Si ox Si Zd r z dr T T T     =     − = −     +      (21) where G is the band gap energy, q is the elementary charge, VGS is the gate to source voltage, VDS is the drain to source voltage, ϕbi is the built-in potential, and VG is the electrostatic gate potential. The relative permittivity of silicon is εSi, whereas silicon dioxide is εox and Tox are short for Silicon and Oxide Thickness, respectively. For each of the three sections of gate metal, we derive a distinct potential by substituting the boundary conditions (19) to (20) in Eq. 2 21 1 1 12 2 22 2 2 1 1 22 2 23 3 3 1 2 1 2 32 ( ) , 0 ( ) , ( ) , s s s s s d z Z L dz d z L Z L L dz d z L L Z L L L dz             − =   − =   + − = +   + + where 2 2 2 2 ln 1 ( ); 1, 2,3 2 ox ox Si n gs FBn Si t R R V V n t R      =   +    = − − = = Impact of High-K Metal Oxide as Gate Dielectric on the Certain Electrical Properties of Silicon … 559 Here the Flat Band voltages are given as [12-15] ( ); 1, 2,3 2 FBn Mn Si g Si Si F V n E q      = − = = + + (22) We arrive at a solution for the surface potential beneath each gate material as, by solving the second order differential equations (21) to (22). 1 1 1 1 12 2 2 2 2 1 1 22 3 3 3 3 1 2 1 2 32 ( ) ; 0 ( ) ; ( ) ; Z Z S Z Z S Z Z S z e e Z L z e e L Z L L z e e L L Z L L L                      − − − = + −   = + −   + = + − +   + + (23) The values for various constants are determined as follows after applying the boundary conditions to the previously mentioned three equations: 2 2 (1 ) (1 ) ; 1, 2,3 ( ) ( 1) ( 1) ; 1, 2 ( ) n n n n n n n n L Ln bi ds n L L L Ln bi ds n L L V e e V n e e V e e V n e e             − − −   − + − +  = =  −       − + − −  = =  −     When we change the aforementioned constants in the above-mentioned equations, we obtain, ( ) ( )   2 1 ( ) sinh( ) sinh ( ) (sinh ) sinh( ) (sinh ) sinh( ) sinh ( ) ; 1,2,3 nS bi n n ds n n n n n z V L L z V L L L z L z n            = + − + +  + + + − = (24) The ratio of the change in drain current to the change in gate voltage is used here to define a device's transconductance. By comparing the drain current to the gate overdrive voltage in this case, we may assess the transconductance (gm). (gm) is calculated as 2 2 2 1 ( ) ( ) D m B Gs t i ii G B imp imp I q qZ g k T q V V V k T e nS R         = = − + − +      (25) The different Analog parameters for Ballistic SiNWs MOSFET are obtained from the above equations. 560 S. K. DAS, B. CHETTRI, P. KARKI, B. KUNWAR, P. CHETTRI, B. SHARMA As well as the lateral electric field is written as, 2 2 2 2 3 3 3 3 2 ( ) 2 ( ) ( )( , ) ( ) ( , ) ( ) | ( , ) ( ) | (1 ) (1 ) ( ) ( 1) ( 1) ( ) i i i i i i i i s kz kzs r R kz kzs r R kL kLi bi ds i kL kL kL kLi bi ds i kL kL d zd r z E z dz dz d r z E z ke ke dz d r z E z ke ke dz M V e e V K e e M V e e V K e e          − = − = − − − − − − = = = = − = = − − + − + = − − + − − = − (26) where, i=1,2,3. The following is the final equation for the electric field distribution for QB SiNW MOSFET     2 ( ) cosh( ) cosh( ( 1)) (cosh( )) cosh( ( )) (cosh( )) sinh( ) bi dsE z V L z L z L V L L           = − − + − − +  (27) The vertical electric field is written as ( )( , ) ( ) log 1 ox G S oxSi Zd r z E r tdr R R         −  = =    +      (28) Total electric field can be obtained as 2 2 z rE E E= + (29) 3. ANALYTICAL RESULTS DISCUSSION Table 1 is a list of the variables used to simulate a ballistic SiNW MOSFET. In addition to elastic scattering, optical phonon emission, and impurity scattering, the effect of these phenomena is explored in the current work. Extensive current-voltage characteristics behaviour at room temperature, among other electrical qualities are reported. The results from the TCAD device simulator validate the model. The TCAD simulator has been utilized to simulate two-dimensional device to assess the accuracy of the suggested analytical model. Among TCAD's offerings, device simulation software is one of the many products available. Impact of High-K Metal Oxide as Gate Dielectric on the Certain Electrical Properties of Silicon … 561 Table 1 The parameters applied in the simulation of ballistic SiNW MOSFET Sl. No Quantities Symbol Value 1 Doping of source NA 1019 cm-3 2 Doping of drain ND 1019 cm-3 3 Doping of channel Ni 1018 cm-3 4 Oxide thickness tox 1nm 5 Channel length L 2nm 6 Channel width W 10nm 7 Channel Hight (H 9nm Fig. 3 ID–VD properties of SiNW MOSFET with high-κ HfO2 act as gate dielectrics When compared to the TCAD simulated results, Fig. 3 shows the simulated values of ID vs.VDS characteristics of SiNW MOSFETs with high-κ HfO2 as gate dielectrics at various gate overdrives (V(gs-t)). Here, the number of electrons in the channel has increased, so ID is gradually increasing while the gate overdrive voltage increases. Fig. 4 illustrates a comparison between the drain current levels of SiNW MOSFETs featuring high-κ HfO2 gate dielectrics and Quasi Ballistic SiNW MOSFETs. It is apparent that the computed values from the analytical model closely align with the simulated values. Through this analysis, we observed that the magnitude of the INB decreases due to an increase in access resistance (Rimp) associated with the current flow. As the potential drop across gate voltage rises, the transconductance of NBM with QB SiNW MOSFET devices rapidly decreases, as shown in Fig. 5. Gate overdrive QB SiNW MOSFET Model. Here, we observed that the linear portion of the ID vs VG curve provided the transconductance. 562 S. K. DAS, B. CHETTRI, P. KARKI, B. KUNWAR, P. CHETTRI, B. SHARMA Fig. 4 ID–VD characteristics of NB SiNW MOSFET with QBM for various Gate voltages Fig. 5 Transconductance vs gate to source voltage of NBM SiNW MOSFET with QBM Transconductance of dispersed SiNW MOSFETs against Gate to Source Voltage at T=300K and 400K is shown in Fig. 6. The ID-VG characteristics' linear region had yielded transconductance. The mobility is reduced and the transconductance is decreased when scattering and temperature effects are combined. It complies that transconductance is inversely correlated to mobility. As the gate voltage rises, the temperature-influenced SiNW MOSFET's transconductance begins to significantly deteriorate. According to Fig. 6, the magnitude of transconductance likewise reduces when temperature rises from 300K to 500K. Transconductance Generation Factor (TGF) with gate overdrive of the combined scattered near ballistic SiNW MOSFET is compared to the quasi-ballistic and ballistic SiNW MOSFET Impact of High-K Metal Oxide as Gate Dielectric on the Certain Electrical Properties of Silicon … 563 models in Fig. 7. The combined scattering effects considerably lower TGF as compared to Natori's models, which were previously studied. In the subthreshold range, the values of TGF for the Near Ballistic and Scattered SiNW MOSFET models are almost identical. Fig. 6 Transconductance of dispersed SiNW MOSFETs against Gate to Source Voltage at Different Temperatures Fig. 7 At a drain voltage of VDS=2V, the near-ballistic SiNW MOSFET transconductance generation factor against gate to source voltage is compared to both the quasi-ballistic and ballistic models 564 S. K. DAS, B. CHETTRI, P. KARKI, B. KUNWAR, P. CHETTRI, B. SHARMA 4. CONCLUSION The I-V characteristics of a Quasi Ballistic (QB) SiNW MOSFET with high-κ HfO2 which act as gate dielectrics were proposed in this work. The model-generated data and the TCAD-simulated data showed an obvious agreement. Utilizing this concept, we formulated an analytical equation for drain current, mainly dependent on drain bias, combined scattered mobility, and carrier energy. Compared to a QBD, our SiNW MOSFET model with high-κ HfO2 exhibits a consistent increase in drain current, albeit with a smaller magnitude. As gate voltage rises, transconductance in our model degrades due to reduced channel mobility, and when scattering and temperature effects are combined, mobility decreases, and transconductance diminishes. This aligns with the known inverse relationship between transconductance and mobility. Moreover, with increasing gate voltage, the temperature-induced decline in SiNW MOSFET transconductance becomes significant, where the TGF values are nearly identical for Near Ballistic and Scattered SiNW MOSFET models in the subthreshold region. Hence, our proposed method is suitable for modeling scattered SiNW MOSFETs in the presence of temperature effects. This study's assumptions regarding the characteristics of high-κ metal oxides or silicon nanowires may not perfectly align with real experimental conditions, potentially affecting result accuracy. The simulation might not encompass the influence of external factors like temperature variations and environmental conditions on electrical properties in practical devices. Additionally, the study may not thoroughly address the complex interfaces between high-κ gate dielectrics and silicon, which can have a substantial impact on device performance. Acknowledgment: The author (Sanat Kumar Das) acknowledges The TMA Pai University Research Fund-Award of Minor Grant, SMIT, SMU, Sikkim (Sanction No.: 6100/SMIT/R&D/Project/12/2020, dated 20th July ,2020). This work is supported by All India Council for Technical Education (AICTE) Govt. of India under Research Promotion Scheme for North-East Region (RPS-NER) vide ref.: File No. 8-139/RIFD/RPS- NER/Policy-1/2018-19 (PI: Bikash Sharma). REFERENCES [1] A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. Mcintyre, P. Mceuen, M. Lundstrom and H. Dai, "High-κ dielectrics for advanced carbon-nanotube transistors and logic gates", Nat. Mater., vol. 1, pp. 241-246, 2002. [2] L. J. Lauhon, M. S. Gudlksen, D. Wang, and C. M. Lieber, "Epitaxial core-shell and core-multishell nanowire heterostructures", Nature, vol. 420, pp. 57-61, 2002. [3] P. F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel and W. 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