12857 FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 38, No 1, March 2025, pp. 109 - 126 https://doi.org/10.2298/FUEE2501109D © 2025 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND Original scientific paper PERFORMANCE ANALYSIS OF PSEUDORANDOM ABSOLUTE POSITION ENCODER WITH EMBEDDED SERIAL PSEUDORANDOM/NATURAL CODE CONVERTER Milan R. Dinčić, Milica S. Stojanović, Goran S. Miljković, Dragan B. Denić University of Niš, Faculty of Electronic Engineering Niš, Department of Measurements, Niš, Serbia ORCID iDs: Milan R. Dinčić https://orcid.org/0000-0001-7508-0277 Milica S. Stojanović https://orcid.org/0009-0000-5528-3675 Goran S. Miljković https://orcid.org/0009-0004-1973-2911 Dragan B. Denić https://orcid.org/0000-0001-5582-0944 Abstract. Pseudorandom absolute position encoders represent an advanced version of the widely used absolute position encoders, particularly suitable for high-resolution angular position measurement. This paper presents a detailed performance analysis of the pseudorandom absolute position encoder with embedded serial pseudorandom/natural code converter, focusing on the maximum operating frequency and the absolute error in angular position measurement. The generalized analysis, applicable to various resolution values, represents a significant contribution of the paper. Determining the maximum operating frequency involves a detailed analysis of propagation delays in the serial code converter circuit. It is demonstrated that encoder resolution profoundly impacts performance, with a dual effect: higher resolution decreases the absolute error but also reduces the maximum operating frequency, necessitating the determination of the most suitable resolution value for each specific application. In addition to its theoretical importance, the generalized analysis aids practical application by facilitating performance calculations and the selection of the most suitable resolution for specific applications. The performance evaluation was conducted for code converters implemented using the widely used 74LVC logic circuits, considering a 6-bit converter as a representative example of converters with a single XOR logic gate in the feedback loop of the shift register, and an 8-bit converter as a representative example of serial converters with three XOR logic gates in the feedback loop. By applying the proposed analysis, the maximum clock frequency was determined to be 29.85 MHz for both resolution values (6 and 8 bits). Simulations in NI Multisim software validate the performed analysis, showing a strong correlation between simulation and theoretical results. Received July 23, 2024; revised October 2, 2024; accepted October 16, 2024 Corresponding author: Milan R. Dinčić University of Niš, Faculty of Electronic Engineering Niš, Aleksandra Medvedeva 14, 18000 Niš, Serbia. E-mail: milan.dincic@elfak.ni.ac.rs https://orcid.org/0000-0001-7508-0277 https://orcid.org/0009-0000-5528-3675 https://orcid.org/0009-0004-1973-2911 https://orcid.org/0000-0001-5582-0944 110 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ Key words: angular position measurement, pseudorandom absolute position encoder, pseudorandom binary sequence, serial pseudorandom/natural code converter, propagation delay analysis 1. INTRODUCTION Absolute position encoders [1-14] are transducers utilized for determining the linear or angular position of a movable system, with numerous applications such as in automotive manufacturing, intelligent robots, aerospace [1], radar systems, machine positioning, printers, mechanical arms, machine health monitoring [2], CNC (computer numerical control) machines [3], integrated circuits manufacturing [2, 4], crane positioning [5], industrial motor shaft positioning [6], scanners, telescopes, process lines and elevators. When focusing on angular position measurement, absolute position encoders typically feature a code disk attached to the rotating system. This disk is divided into distinct angular sectors, each corresponding to a unique n-bit binary code word, where n represents the encoder's resolution. In commonly used optical absolute encoders, the bits of these code words are represented on the code disk by transparent and opaque (or reflective and non-reflective) fields. The current angular sector of the rotating system is identified by reading the corresponding code word from the code disk using LED diodes and phototransistors [1]. Absolute position encoders offer significant advantages over other angular position sensors, such as potentiometers, synchros, resolvers, and rotary variable differential transformers, by providing direct digital information and eliminating the need for analog-to-digital conversion [15]. Additionally, they can immediately provide angular position information upon power restoration, unlike incremental encoders that require initialization to a reference position [1, 3, 7, 8]. Classic absolute encoders typically use Gray (or natural) binary code [6], necessitating n concentric code tracks on the code disk and n optical reading heads for an n-bit absolute position encoder. Thus, as the resolution increases, the complexity also rises, making it challenging to apply classic absolute encoders in emerging high-resolution applications, which is their main drawback [8, 16]. Pseudorandom absolute position encoders [3, 5, 8, 17-21] are an advanced type of encoders that use pseudorandom code words inscribed along a single code track on the code disk to encode angular sectors. These code words are part of a pseudorandom binary sequence (PRBS) of maximum length, known as an m-sequence [22-25], generated using a linear feedback shift register (LFSR) [26-31]. Since two consecutive pseudorandom code words in an m-sequence differ by only one bit, detecting only that bit is required, with the rest inferred from the previous code word, allowing the use of a single reading head [5, 8, 19]. Thus, the pseudorandom encoder design, which includes a single code track and one reading head regardless of resolution, maintains low complexity even as resolution increases. This simplifies the implementation of high-resolution encoders, which is their primary advantage [8]. Additionally, pseudorandom encoders enhance reliability by enabling the implementation of error detection methods [21] and allow for direct zero position adjustment after the code disk is mounted on the shaft [17]. However, a notable challenge arises from the incompatibility of pseudorandom code words with conventional digital electronics, necessitating their conversion into natural binary code. Two primary types of pseudorandom/natural code converters are employed for this purpose: the serial converter [8, 18, 20], which utilizes a shift register, and the parallel converter [8], retrieving code words from ROM memory. This paper considers the serial code converter, widely used in practical applications due to its simplicity Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 111 and ability to facilitate direct zero position adjustment with minimal hardware or software modifications [17]. An absolute position encoder identifies the current angular sector of the rotating system but may not pinpoint the exact position within it, which can lead to measurement errors. The maximum absolute error in angular position measurement is one of the crucial performance metrics for pseudorandom absolute position encoders. Equally significant is their maximum operating frequency, which indicates the highest rotational speed (measured in rotations per second) at which the encoder can accurately determine the current angular sector. The paper thoroughly examines the performance of the pseudorandom absolute position encoder with an embedded serial pseudorandom/natural code converter, focusing on its maximum operating frequency and maximum absolute error in angular position measurement. The study finds that the maximum operating frequency depends on the maximum clock frequency of the serial code converter, which in turn is determined by its maximum propagation delay. Starting with an analysis of the propagation delay within the serial code converter circuit, the paper derives an expression for its maximum clock frequency. It then extends to derive equations for the maximum operating frequency of the encoder and its maximum absolute error in angular position measurement. It should be emphasized that these analyses are conducted in a generalized manner to accommodate any resolution value, thereby enhancing their significance and broad applicability. The performance of the encoder is assessed for two resolution values (6 and 8 bits), assuming the implementation of the serial code converter using logic gates from the 74LVC family. To validate the analysis, simulations of the serial code converter are performed using NI Multisim software [32], standardly used in research and industry for analyzing the real behavior of electronic circuits. The simulation results closely match the theoretical outcomes, confirming the correctness of the analysis. The theoretical analysis and numerical results outlined in the paper indicate that increasing the resolution affects the pseudorandom absolute position encoder in two ways. First, it lowers the maximum operating frequency, which poses a challenge. However, it also reduces the maximum absolute error in angular position measurement, which is advantageous. Hence, determining the most suitable resolution value tailored to the specific application is crucial, as it balances accuracy requirements and expected rotation speeds of the system. Beyond its substantial theoretical contribution in formulating generalized expressions for the performance of pseudorandom absolute position encoders, the paper also carries notable practical implications, as the derived expressions enable the assessment of performance across different resolution values, facilitating the selection of the most suitable resolution value for each specific application. The paper is organized as follows. Section 2 presents the generators of direct and inverse PRBS, while Section 3 provides a detailed description of the serial pseudorandom/natural binary code converter. Section 4 focuses on the analysis of propagation delay in the circuit of the serial pseudorandom/natural code converter, while Section 5 provides the performance analysis of the pseudorandom absolute position encoder. Numerical and simulation results for the serial code converter implemented by logic circuits from the 74LVC family are presented in Section 6, while Section 7 concludes the paper. 112 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ 2. GENERATORS OF DIRECT AND INVERSE PRBS A PRBS of maximum length, known as m-sequence, with a resolution of n, is a cyclic binary sequence with a period of 2n − 1 bits. It is generated by an n-bit linear shift register comprising n D-type flip-flops (FF1, ..., FFn), with a feedback branch [26-29], as illustrated in Fig. 1a. Bits of PRBS are obtained at the output of the last flip-flop FFn. The number of different states of the shift register is 2n − 1 rather than 2n , since the all-zero state is not allowed; if it were, the shift register would never be able to exit that state. PRBS generation starts from an initial (reference) state of the shift register, where any of the allowed 2n − 1 states can be selected as the reference state. With each clock cycle, the shift register moves to a new state, producing one PRBS bit until it completes 2n − 1 clock cycles encompassing all possible states and returns to the reference state. Each n-tuple of consecutive PRBS bits forms a unique code word, with the total of 2n − 1 different n-bit code words within one PRBS period. Each code word is equal to a distinct state of the shift register. a) b) Fig. 1 Generator of direct PRBS for a) an arbitrary resolution n; b) resolution n = 6 Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 113 Inputs of flip-flops FFi (i = 2, …, n) are obtained directly from the outputs of the previous flip-flops FFi-1, while the input to FF1 is derived as a linear combination of flip-flops’ outputs, generated by the feedback branch, comprising XOR logic gates implementing modulo 2 summation. The structure of the feedback branch, including the number and position of XOR logic gates, is pivotal for the design of the PRBS generator. Only with a specific structure of the feedback branch, the shift register can traverse through all 2n − 1 possible states, producing a PRBS of maximum length of 2n − 1 bits; otherwise, shorter sequences are generated. The feedback branch structure for a shift register of length n, producing the maximum length PRBS, is determined by binary coefficients ci (i = 1, …, n-1) of the primitive generator polynomial Pn (X) of degree n, defined as [26-29]: ( ) 1 1 1 1.n n n nP X X c X c X− −= + + + + (1) The binary coefficient ci (i = 1, …, n-1) determines whether the output of the i-th flip-flop FFi contributes to the modulo 2 summation; if ci = 1, the output of FFi participates in modulo 2 summation, otherwise it does not. With r coefficients equal to 1, there are r XOR logic gates in the feedback branch. If Xi represents the bit written in the i-th flip-flop FFi, the state of the shift register of the direct PRBS generator is marked as Xn Xn-1 … X1, implying that bits are observed from the last flip-flop (FFn) towards the first (FF1). The reference state is denoted as 0 0 0 1 1n nX X X− . For the resolution n = 6, the generator polynomial has the form P6 (X) = X6 + X5 + 1, giving the coefficients’ values c5 = 1, c4 = c3 = c2 = c1 = 0. The direct PRBS generator for resolution n = 6 is shown in Fig. 1b. Since only one coefficient is equal to 1, there is only one XOR logic gate in the feedback branch. An essential aspect of implementing the serial Fibonacci code converter is the existence of an inverse sequence corresponding to each direct PRBS of maximum length, which resembles a mirror image of the direct sequence. The inverse sequence generator for arbitrary resolution n, depicted in Fig. 2a, comprises an n-bit shift register with a feedback branch, resembling the direct PRBS generator but with notable distinctions: ▪ the feedback branch of the inverse PRBS generator is structured similarly to the direct PRBS according to the generator polynomial Pn (X) defined in (1). The difference is that the coefficient cn-i (i = 1, …, n−1) corresponds to the output of the i- th flip-flop FFi; if cn-i = 1, the output of FFi contributes to the modulo-2 summation, otherwise it does not; ▪ bits of the inverse PRBS are taken from the input of the first flip-flop FF1; ▪ if Yi indicates the bit of the i-th flip-flop (FFi) within the shift register of the inverse PRBS generator, the shift register's state is denoted as Y1Y2 … Yn, with bits observed from the first flip-flop (FF1) to the last (FFn); ▪ if 0 0 0 1 2 nY Y Y is designated as the initial (reference) state of the shift register, serving as the starting point for generating the inverse PRBS, then 0 0 0 1 2 nY Y Y = 0 0 0 1 1n nX X X− , meaning that the inverse PRBS originates from the identical reference state as the corresponding direct PRBS, with the distinction that the bits are entered into the shift register in reverse order, i.e. 0 0 1i n iY X + −= , i = 1, …, n . Fig. 2b shows the inverse PRBS generator for a resolution of n = 6. When the reference state is set to 111100 for n = 6, the generator depicted in Fig. 1b produces the direct PRBS: 114 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ 111100000100001100010100111101000111001001011011101100110101011, while the generator depicted in Fig. 2b generates the corresponding inverse PRBS: 110101011001101110110100100111000101111001010001100001000001111. These sequences clearly exhibit mirror symmetry. a) b) Fig. 2 Generator of inverse PRBS for a) an arbitrary resolution n; b) resolution n = 6 An important characteristic of the inverse PRBS generator is that its shift register, starting from the specified reference state, traverses all permissible states but in reverse order, compared to the shift register in the direct PRBS generator. For instance, the Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 115 following are some of the states through which the shift registers progress in both the direct and inverse PRBS generators while generating one PRBS period, considering a resolution of n = 6 and the reference state 111100: ▪ states of the shift register in the direct PRBS generator: 111100, 111000, 110000, 100000, 000001, 000010, 000100, 001000, 010000, ..., 101010, 010101, 101011, 010111, 101111, 011111, 111111, 111110, 111100; ▪ states of the shift register in the inverse PRBS generator: 111100, 111110, 111111, 011111, 101111, 010111, 101011, 010101, 101010, ..., 010000, 001000, 000100, 000010, 000001, 100000, 110000, 111000, 111100. After passing through 63 different states, both the direct PRBS generator and the inverse PRBS generator return to the initial (reference) state 111100 (which is underlined to indicate the beginning of a new PRBS period). 3. DESCRIPTION OF THE SERIAL PSEUDORANDOM/NATURAL BINARY CODE CONVERTER An important element on an n-bit pseudorandom absolute position encoder is the code disk, affixed to the rotating system whose angular position is being measured. The code disk is divided into 2n − 1 angular sectors, each corresponding to a unique n-bit pseudorandom code word within a direct PRBS of 2n − 1 bits written along the edge of the code disk. The angular position is measured relative to some zero (reference) sector, encoded with a reference code word 0 0 0 1 2 nY Y Y , To ascertain the current angular sector of the rotating system (i.e. the distance from the reference sector), the initial step involves reading the pseudorandom code word Y1Y2 …Yn from the code disk corresponding to that specific sector. As digital electronics cannot process pseudorandom code words directly, the read n-bit code word requires conversion into an n-bit code word of the natural binary code. The serial pseudorandom/natural code converter [8, 18, 20], whose block diagram is shown in Fig. 3 for an arbitrary resolution n, is one of the most widely utilized methods for converting pseudorandom code into natural binary code. It operates on the principle that each direct PRBS has a corresponding inverse PRBS. The inverse PRBS generator, which produces the inverse PRBS relative to the PRBS encoded on the code disk, is at the core of the serial code converter. The following is a brief overview of how the serial code converter operates. The read code word Y1Y2 …Yn is entered into the n-bit shift register of the inverse PRBS generator within the code converter. Starting from state Y1Y2 …Yn , the shift register transitions to a new state at each clock cycle, traversing states in reverse order compared to the direct PRBS generator, thereby approaching the reference state 0 0 0 1 2 nY Y Y . When the shift register reaches the reference state, the code conversion is completed. The serial code converter incorporates an n-bit counter that counts clock cycles from the start of the conversion. The output of the counter, at the moment when the shift register reaches the reference state, is an n-bit code word P1P2…Pn in natural binary code, representing the distance between the read code word Y1Y2 …Yn and the reference code word 0 0 0 1 2 nY Y Y . This provides the distance between the current and reference sectors, which was intended to be measured. The code word P1P2…Pn is written into the output register as the result of the serial code conversion. 116 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ Fig. 3 The block diagram of the serial pseudorandom/natural code converter for an arbitrary resolution n The serial code converter also includes several other essential elements crucial for its proper functioning. Firstly, the NAND1 logic gate is used to determine whether the shift register has reached the reference state. The inputs to the NAND1 gate come from the outputs of flip-flops within the shift register. If the i-th bit of the reference code word is equal to 1, the output of the corresponding flip-flop is directly linked to the NAND1 gate. Conversely, if it is 0, the output of the i-th flip-flop is inverted by a NOTi inverter before reaching the NAND1 gate. Consequently, the NAND1 gate outputs a logic 0 only when the shift register reaches the reference state; otherwise, it outputs logic 1. Fig. 3 is drawn Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 117 for the case where the reference code word is 111...10, composed of all ones except for the last bit, which is 0, resulting in a direct connection between the outputs of all flip-flops and the NAND1 gate, except for the last flip-flop (FFn), whose output is inverted before reaching the NAND1 gate. If the output of the NAND1 gate is 0, the corresponding γ bit at the output of the ANDγ gate is also set to 0, indicating the completion of the current pseudorandom code word conversion. At this point, the counter's current content is transferred to the output register as the resultant natural binary code word, and the counter resets to 0, preparing it for the next conversion cycle. In the next clock cycle, conversion of a new pseudorandom code word read from the code disk begins by writing its bits into the flip-flops of the shift register. It was previously mentioned that a shift register state consisting of all zeros is prohibited since the shift register cannot exit that state. In normal operation, the shift register avoids entering such a state. However, there is a possibility that during the startup of the serial converter the shift register may initially find itself in an all-zero state, hindering proper operation. To address this, a NAND0 logic gate is integrated into the converter circuit, with its inputs linked to the inverted outputs of all flip-flops. If the shift register encounters an all-zero state during startup, the NAND0 gate outputs logic 0, triggering γ = 0, which commences writing bits of the read code word into the flip-flops. This action enables the shift register to exit the all-zero state and operate correctly. After startup, the NAND0 no longer has any influence, with only the NAND1 gate influencing the γ bit value. There are three logic gates (ANDi,1, ANDi,2 and ORi) at the input of each flip-flop FFi (i = 1, …, n) in the shift register, responsible for managing the bit-writing process. Specifically, when γ = 1, the conversion of the current pseudorandom code word is not finished yet and bits obtained by the shifting process of the shift register are written into the flip-flops through ANDi,1 and ORi gates. Conversely, when γ = 0, the conversion of the next pseudorandom code word begins by writing its bits into the flip-flops through ANDi,2 and ORi gates. To better explain the Fibonacci code converter, its operation will be considered for a specific 6-bit resolution, as depicted in Fig. 4. Its core component is the inverse PRBS generator from Fig. 2b. For the sake of illustration, let Y1Y2...Y6 = 001000 represent the read pseudorandom code word to be converted into natural binary code, and let 0 0 0 1 2 6Y Y Y = 111100 serve as the reference pseudorandom code word. Initially, the read pseudorandom code word is loaded into the shift register. Subsequently, with each clock pulse, the shift register transitions to a new state, progressing through the following states: 001000 → 000100 → 000010 → 000001 → 100000 → 110000 → 111000 → 111100. By the 8th clock pulse, the shift register reaches the reference state 111100. Counting from 0, after 8 clock pulses the counter will increment up to 7; its content will be P1P2…P6 = 000111, which is the resulting code word of the natural binary code, representing the value of position p = 7. A pseudorandom/natural code converter for a resolution of n = 8 is shown in Fig. 5. Compared to Fig. 4, the difference lies in the feedback circuit. For a resolution of n = 8, the generator polynomial has the form P8(X) = X8 + X6 + X5 + X2 + 1. In this case, three coefficients are equal to 1, resulting in 3 XOR logic gates in the feedback branch. 118 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ Fig. 4 The block diagram of the serial pseudorandom/natural code converter for resolution n = 6 Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 119 Fig. 5 The block diagram of the serial pseudorandom/natural code converter for resolution n = 8 120 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ 4. ANALYSIS OF PROPAGATION DELAY IN THE CIRCUIT OF THE SERIAL PSEUDORANDOM/NATURAL CODE CONVERTER Let AND, OR, NAND and NOT denote propagation delays of AND, OR, NAND and NOT gates, respectively. Considering the propagation delays of the D flip-flop, let FF setup denote the amount of time before the rising edge of the clock pulse during which the signal at the D input of the flip-flop must remain stable, while FF QCLK→ denote the amount of time after the rising edge of the clock pulse required for the flip-flop to produce a change at the output Q. Bits are written into the flip-flops at the rising edge of the clock signal. Therefore, all propagation delays in the circuit are measured relative to the rising edge of the clock. The data path to obtain the bit γ is: flip-flops → NOTi gates → NAND1 gate → ANDγ gate. Hence, the propagation delay for obtaining the bit is: ANDNANDNOT FF QCLKγ  +++= → . (2) If γ = 1, the conversion of the current pseudorandom code word continues by writing bits obtained through the shifting process of the shift register into the flip-flops using ANDi,1 and ORi logic gates. Let ai denote one input bit of the ANDi,1 gate (i = 1,...,n) obtained through the shifting process of the shift register, while the second input bit of the ANDi,1 gate is the bit γ. Let ai denote propagation delay to obtain the bit ai. The data path to obtain the bit a1 (which is one input of the AND1,1 gate) is: flip-flops → feedback circuit, producing the propagation delay XOR FF QCLK1  += → ka , since the feedback circuit consists of k XOR logic gates connected in series. Bits ai (i = 2,...,n) are obtained directly from the output of the previous flip-flop FFi-1, producing the propagation delay FF QCLK→= ia . If a denotes the maximum propagation delay for obtaining all the bits ai (i = 1,...,n), according to the previous analysis, it follows that: XOR FF QCLK 1 1 }{max  +=== →  kaa ni a i . (3) Hence, for γ = 1, the delay required for all the bits obtained by the shifting process to be ready for writing into the D inputs of the flip-flops through 1,ANDi and iOR gates is: FF setupANDNANDNOTXORORAND FF QCLK FF setupORANDγ 1γ },max{ },max{   ++++++= +++= → = k aD . (4) If γ = 0, a new conversion starts by writing bits of a new pseudorandom code word into the flip-flops through ANDi,2 and ORi gates. The bits of the new pseudorandom code word Y1Y2...Yn are ready at the inputs of the ANDi,2 gates, but the formation of the bit γ (inverted γ bit) needs to be awaited, serving as the second input of the ANDi,2 gates. The propagation delay to obtain the bit γ is NOTγγ  += . Let 0γ= D represent the time delay measured from the beginning of the current clock pulse, required for the bits of the new code word to be written into the D inputs of the flip-flops, for γ = 0: FF setupORANDNANDNOT FF QCLK FF setupORANDγ 0γ 22  +++++=+++= → = D . (5) Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 121 For the counter, the following delays are of particular interest: counter QCLK→ - the delay between the start of the clock pulse and the change in the counter output; counter setup - the minimum time the signal at the counter's input must remain stable before the rising edge of the clock; and counter QR→ - the time needed for the counter to reset after receiving a signal at the R input. When γ is equal to 1, the conversion is in progress, and the counter is in normal counting mode; hence, the delays of interest are counter QCLK→ and counter setup . When γ becomes 0, the converter has reached the reference state and the counter is resetting, making the delay of interest counter QR→ . According to the previous analysis, the maximum delay in the serial code converter circuit for the case when γ = 0 is given by: γ 0γ 0 counter R Qmax{ , }D  == →= , (6) whereas when γ = 1, the maximum delay is given by: γ 1γ 1 counter counter CLK Q setupmax{ , }D   == →= + . (7) Finally, the maximum propagation delay of the serial code converter circuit is: },max{ 1γ0γ max ===  . (8) 5. PERFORMANCE ANALYSIS OF THE PSEUDORANDOM ABSOLUTE POSITION ENCODER This section delves into the examination of two crucial performance metrics related to pseudorandom absolute position encoders: the maximum operating frequency and the maximum absolute error. It is important to emphasize that this analysis is generalized, ensuring its validity across various resolution values. 5.1. Maximum operating frequency of the pseudorandom absolute position encoder The conversion of a pseudorandom code word, which is p positions away from the reference code word, will require (p + 1) clock cycles: one clock cycle to write the code word into the shift register of the converter, followed by an additional p clock cycles to reach the reference state. Starting from 0, the counter reaches the value of p after (p + 1) clock cycles. The duration of the conversion is: clockTp += )1( , (9) where T clock is the period of the clock pulses of the converter and f clock = 1/T clock is clock frequency. The longest conversion time occurs for the code word that is furthest from the reference code word, i.e., corresponding to the maximum position pmax = 2n − 2, and is equal to: clocknclock TTp −=+= )12()1( maxmax . (10) Let f denote the rotation frequency (i.e., the number of revolutions per second) of the rotating system whose angular position is being measured. Then, T = 1/f represents the 122 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ rotation period, i.e., the time it takes for the rotating system to complete one full revolution. For a resolution of n, the time it takes for the rotating system to traverse the width of one angular sector is: )12( 1 12 − = − = nn f T  , (11) which essentially represents the time interval between the readings of two consecutive code words from the code disk. In order for the pseudorandom absolute position encoder to function properly, the conversion of the current pseudorandom code word must be completed before a new code word is read. Therefore, the following condition must be satisfied:  max , (12) meaning that the maximum conversion duration must be shorter than the time between the readings of two consecutive code words. Based on (10), (11) and (12), the following is obtained: )12( 1 )12( − − n clockn f T . (13) From (13), it follows that: clockn T f −  2)12( 1 . (14) The maximum operating frequency fmax, at which the pseudorandom absolute position encoder can function correctly for a given resolution n, based on (14), is: clockn T f min 2max )12( 1 − = , (15) where clockTmin represents the minimum allowed value of the clock period. For the serial code converter to function correctly, the clock period must not be shorter than the maximum propagation delay in the code converter circuit max, defined by (8), implying that: clockTmin = m ax . (16) Hence, the maximum allowed frequency of the clock pulses is: maxmin max 11  == clock clock T f . (17) Based on (15) and (16), the final expression for the maximum operating frequency is obtained: max 2max )12( 1 − = n f . (18) Based on (18), it can be concluded that the maximum operating frequency of the pseudorandom absolute position encoder fmax is inversely proportional to the resolution n and significantly decreases as n increases. For a given resolution n, fmax depends on the maximum propagation delay max in the code converter circuit: the smaller the max, the larger the fmax will be. Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 123 5.2. Absolute error of angular position measurement Using pseudorandom absolute encoders, the angular sector in which the rotating system is located can be determined, but the exact angular position within that sector cannot. Considering that the angular position is measured in the middle of angular sectors, the maximum absolute error in measuring the angular position equals half the width of an angular sector: )12(2 360 m ax − = n  . (19) It can be seen that as the resolution n increases, the absolute error significantly decreases. 6. NUMERICAL AND SIMULATION RESULTS From expressions (2) through (8), it is observed that changing the resolution n only affects the parameter k, which represents the number of XOR gates in the feedback loop of the shift register, while all other parameters that influence the maximum propagation delay remain the same. For each specific resolution value n, different m-sequences can be generated using various generator polynomials, each with a distinct k value. However, to streamline practical implementations and reduce complexity, cost, and delay, the minimal value of k is commonly used for each specific resolution. Analysis of generator polynomials for all resolutions n of interest (ranging up to several tens) shows that the minimal k value can either be 1 or 3, depending on the resolution n [26-29]. Therefore, two resolutions will be considered: n = 6, as a representative example of a serial converter with one XOR logic gate in the feedback loop of the shift register, and n = 8, as a representative example of a serial converter with three XOR logic gates in the feedback loop. To evaluate the performance of these code converters, they were implemented using the widely used 74LVC family of logic circuits. The typical propagation delays for these circuits are: AND = 4.1 ns, OR = 3.8 ns, NAND = 6.3 ns, NOT = 4 ns, XOR = 5 ns, FF setup = 7.4 ns, FF QCLK→ = 5.2 ns, counter setup = 2.5 ns, counter QCLK→ = 7.3 ns and counter QR→ = 6.4 ns. Theoretical values for the maximum clock frequency clockfmax of the serial code converter derived from expression (18), and the maximum operating frequency of the pseudorandom encoder fmax defined by (19), are detailed in Table 1, for resolutions n = 6 and n = 8. To validate the theoretical results, simulations of the considered 6-bit and 8-bit serial code converters were performed using NI Multisim, an industry-standard SPICE simulation tool for analog and digital electronics, which enables the analysis of functionality and propagation delays. The layout of the 6-bit serial code converter, as implemented in the Multisim simulator, is shown in Fig. 6. Multisim facilitates simulations across different clock frequencies, with the aim to determine the maximum clock frequency clockfmax at which the serial code converter functions correctly. The values of clockfmax obtained from these simulations are also presented in Table 1. Table 1 also shows the maximum absolute error values max for angular position measurement with the pseudorandom absolute encoder, at resolutions of n = 6 and n = 8. 124 M. R. DINČIĆ. M. S. STOJANOVIĆ, G. S. MILJKOVIĆ, D. B. DENIĆ Fig. 6 Simulation of the serial pseudorandom/natural code converter in NI Multisim software for resolution n = 6 Table 1 Performance of the 6-bit and 8-bit serial code converters obtained by theory and by simulations n k Theory/Simulation max clockf maxf max 6 1 Th. 29.85 MHz 7.4 kHz 2.86 ° Sim. 28.98 MHz 8 3 Th. 29.85 MHz 457.27 Hz 0.71 ° Sim. 28.98 MHz From Table 1, it can be seen that the theoretical and simulation values of clockfmax are very close, indicating that the simulations validate the theoretical analysis. The slight difference between the theoretical and simulation values of clockfmax is expected, as the actual delays of logic gates are never exactly the same as the given values but vary within a certain range around them. Furthermore, Table 1 shows that the values of clockfmax for n = 6 and n = 8 are identical. This is because increasing the number of XOR logic gates from 1 to 3 in the feedback loop of the shift register did not increase the maximum propagation delay, as other logic gates in the serial converter circuit predominantly influence it. Based on (18) and (19) and the results in Table 1, it can be concluded that increasing the resolution n reduces the absolute measurement error in angular position max, which is advantageous. However, it also decreases the maximum frequency of the pseudorandom Performance Analysis of Pseudorandom Absolute Position Encoder with Embedded Serial Code Converter 125 absolute position encoder fmax, which is a drawback. Therefore, it is crucial to find the optimal value of resolution n for each specific application, considering both the required accuracy of angular position measurement and the desired maximum rotation frequency. 7. CONCLUSION The paper is dedicated to determining the maximum clock frequency of the serial pseudorandom/natural code converter, as well as the performance metrics (maximum operating frequency and maximum absolute error) of the pseudorandom absolute position encoder. Initially, the paper provides a comprehensive explanation of the structure and operating principles of the serial code converter. Subsequently, an expression for the maximum clock frequency is derived through an in-depth analysis of propagation delays across all paths within the serial converter circuit. Additionally, expressions for the maximum operating frequency and maximum absolute error of the pseudorandom encoder are derived. Notably, the analysis is conducted in a generalized manner, applicable to any resolution value, thus ensuring broad applicability. Assuming the implementation of the serial code converter using 74LVC family logic circuits, the maximum clock frequency values are determined based on theoretical analysis and simulations conducted using Multisim software. The close agreement between the theoretically derived and simulated maximum clock frequency values confirms the accuracy of the theoretical analysis. The analysis conducted in this paper has shown that the main factor affecting the propagation delay of the serial code converter is the logic circuits for writing bits into the flip-flops of the shift register and detecting the reference state, rather than the shift register's feedback branch. This was supported by numerical results (theoretical and simulated), yielding identical maximum clock frequencies for two possible values (1 or 3) of the number of XOR logic gates in the feedback branch of the shift register. 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