13032 FACTA UNIVERSITATIS Series: Electronics and Energetics Vol. 37, No 4, December 2024, pp. 609 – 617 https://doi.org/10.2298/FUEE2404609B © 2024 by University of Niš, Serbia | Creative Commons License: CC BY-NC-ND Original scientific paper DETERMING THE CHARACTERISTICS OF THE LOCALIZED DENSITY OF STATES DISTRIBUTION PRESENT IN MOS2 2D FETS Anisleidy Broche1, Antonio Cerdeira1, Benjamín Iñiguez2, Magali Estrada1 1 SEES, Department of Electrical Engineering, CINVESTAV-IPN, Av. IPN 2208, CP 07360, Mexico City, Mexico 2 Department of Electronics, Electrical and Automatic Engineering, Universitat Rovira i Virgili, Av. Països Catalans 26, Tarragona 43007, Spain ORCID iDs: Anisleidy Broche https://orcid.org/0009-0001-6611-0718 Antonio Cerdeira https://orcid.org/0000-0002-2114-2468 Benjamín Iñiguez https://orcid.org/0000-0002-6504-7980 Magali Estrada https://orcid.org/0000-0002-6244-6492 Abstract. The behaviour of MoS2 FETs, with channel lengths greater than the mean free path of carriers was analysed. Electrical behaviour of experimental devices with channel lengths of 5 m and 0.1 m was studied, modelled and simulated, concluding that the predominant transport mechanism observed was hopping. The presence of a localized density of states (DOS) distribution in the semiconductor layer, causing the behaviour observed in these devices, was studied and determined by both modelling and simulation. Key words: DOS in MoS2 2D FET, mobility of MoS2 2D FETs, MoS2 2D FET modelling and simulation 1. INTRODUCTION In the last years, the possibility of using 2D semiconductors to continue further scaling of metal-oxide-semiconductor field effect transistors has attracted much attention. The use of silicon multi-gate devices seems to be reaching their limit, reason why other approaches are being analysed [1]. To overcome the limitations in further scaling of 3D semiconductor devices, related to the so-called short channel effects, the use of two-dimensional (2D) semiconductor materials seems an interesting approach [2,3]. Received September 20, 2024; revised October 22, 2024 and October 27, 2024; accepted October 29, 2024 Corresponding author: Magali Estrada SEES, Department of Electrical Engineering, CINVESTAV-IPN, Av. IPN 2208, CP 07360, Mexico City, Mexico E-mail: mecueto@yahoo.com https://orcid.org/0009-0001-6611-0718 https://orcid.org/0000-0002-2114-2468 https://orcid.org/0000-0002-6504-7980 https://orcid.org/0000-0002-6244-6492 610 A. BROCHE, A. CERDEIRA, B. IÑIGUEZ, M. ESTRADA The electrostatic characteristics of FET devices described by Poisson equation can be analysed using a parameter called characteristic channel length defined as [4]: 𝜆 = √(𝑥𝑠𝑥𝑖) 𝑘𝑠 𝑘𝑖 (1) where ks and ki, the relative dielectric constants and xs and xi the thickness of the semiconductor layer and insulator, respectively. From the above equation, the characteristic channel length can be reduced by reducing the thickness of the semiconductor or of the insulator layer, or by increasing the relative dielectric constant of the insulator layer. However, with the reduction of the bulk semiconductor layer xs, the electrostatic control of carriers in the channel is reduced, since for example, surface dispersion increases, affecting mobility. In two-dimensional (2D) semiconductor materials, however, it is possible to confine electrons within a very thin channel formed by one or few monoatomic layers. It has been reported that carriers can be uniformly controlled by the gate voltage [2,3]. In principle, if the channel length of the transistor is less than the mean free path of carriers, in the order of or less than 20 nm, ballistic transport mechanism can be observed [5]. Several 2D semiconductor materials are being studied, among which dichalkogenide transition metals (TMDs) with a bandgap above 1 eV, as MoS2, are among the most studied 2D materials for FET devices [3]. At present, 2D FETs with quite good characteristics, for channel lengths greater than the mean free path of carrier, have been already reported, [6-9]. At the same time, several compact models have also been developed for or applied to them [10-14]. It is interesting to notice that several of these models have satisfactorily considered a potential dependence of mobility with gate voltage, which is usually related to the presence of variable range hopping (VRH) as the main transport mechanism, even though the 2D semiconductor layer used, is expected to be crystalline. The hopping mechanism of charge transport describes the movement of charge in the material by hopping between localized states present in the material. This transport mechanism is typical of disordered materials, as polycrystalline or amorphous. However, it can also be observed in crystalline materials, when a sufficiently high density of defects is present. A detailed analysis of the characteristics of mono and several layers films, deposited using different deposition methods, have revealed the presence of defects, that can explain the presence of the hopping mechanism observed. For example, Ghatak et al., studied the low-temperature electrical transport in monolayer, bilayer, and tri-layer MoS2 transistors exfoliated onto Si/SiO2 substrates, determining that, at room temperature, electrons are localized in the ultrathin MoS2 layer and display VRH. They relate this behaviour to charges trapped at the MoS2_SiO2 interface, producing random potential fluctuations [15]. In [16], authors observed grains and grain boundaries in what they called highly crystalline monolayer molybdenum disulfide, arriving to the conclusion, that they were the reason of localized DOS, present in the layers deposited by CVD. In [17-20], authors studied the presence of different defects, in TMD deposited layers, and their effects on the electrical properties of the devices, some of which can be represented as localized states within the bandgap. Determing the Characteristics of the Localized Density of States Distribution Present in MoS2 2D FETs 611 In this work, we analyse the electrical behaviour of MoS2 monolayer FETs, using simulation and modelling techniques. After reproducing their electrical characteristics, we determined and discussed the presence of a density of state (DOS) distribution in the gap of the semiconductor layer that can explain the observed behaviour. The characteristics of the localized DOS are reported. 2. MOS2 2D FETS: STRUCTURE AND MODELLING For the analysis we used two bottom gate 2D FETs, T1 with a channel length of 5 m and T2 with 100 nm. The fabrication process started with a highly dopped P-type silicon wafer used as the substrate, on top of which an Al2O3 layer with 22 nm equivalent oxide thickness (EOT) was deposited. A MoS2 monolayer, of around 1 nm thick, previously deposited by Metal Organic Epitaxial Chemical Vapor Deposition, (MOCVD) on top of a sapphire substrate, was exfoliated and deposited on top of the Al2O3 layer. Lithography was used to define the area of the semiconductor layer. Afterwards Mo was deposited for the drain and source contacts, followed by another lithographic process to define the channel length and drain and source regions [6]. The structure cross section is shown in Fig. 1. Main structure parameters are shown in Table 1. Fig. 1 Cross section of the device Table 1 Structure parameters Structure parameters T1 T2 2D material MoS2 MoS2 Deposition method MOCVD MOCVD Exfoliation Yes Yes Channel width [µm] W 5 5 Channel length [µm] L 5 0.1 2D layer thickness [nm] ts 0.9 0.9 EOT [nm] 22 22 Structure Bottom gate Bottom gate For analysing the transport mechanism observed in the 2D transistors, we modelled their electrical characteristics using the following expressions in Unified Model and Extraction Method (UMEM) developed for Thin Film Transistors (TFTs) [21]. The field effect mobility µFE is calculated as: 𝜇𝐹𝐸 = 𝜇0 𝑛𝑓𝑟𝑒𝑒 𝑛𝑙𝑜𝑐𝑎𝑙𝑖𝑧𝑒𝑑 ~ (𝑉𝐺 − 𝑉𝑇)𝛾𝑎 = 𝜇0 ( 𝑉𝐺−𝑉𝑇 𝑉𝑎𝑎 ) 𝛾𝑎 = 𝜇1(𝑉𝐺 − 𝑉𝑇)𝛾𝑎 (2) 612 A. BROCHE, A. CERDEIRA, B. IÑIGUEZ, M. ESTRADA where µ0 is an adjustment parameter; nfree is the free charge concentration; nlocalized is the localized charge concentration, and nfree < nlocalized. After mathematical arrangements, mobility can be expressed as a power-law function, where VT is the threshold voltage and γa is the field effect mobility parameter. Both are extracted as indicated in [21]. µ1 is the field-effect mobility when VG-VT= 1, expressed as: 𝜇1 = ( 𝜇0 𝑉𝑎𝑎 𝛾𝑎 ) (3) where µo=1 cm2/Vs and Vaa is a model parameter to be extracted calculating from the experimental data 𝐼𝐷𝑆 ( 1 1+𝛾𝑎 ) vs.(𝑉𝐺𝑆 − 𝑉𝑇), its slope Sl and K=(W*Ci)/L: 𝑉𝑎𝑎 = 𝐾𝑉𝐷𝑆 𝑆𝑙1+𝛾𝑎 1 𝛾𝑎⁄ (4) The final current model for above threshold, in linear and saturation regions of operation, for above-mentioned TFT transistors is similar as for MOSFETs [21]: 𝐼𝐷 = 𝑊 𝐿 𝐶𝑖 𝜇𝐹𝐸 (𝑉𝐺−𝑉𝑇) 1+𝑅 𝑊 𝐿 𝐶𝑖 𝜇𝐹𝐸(𝑉𝐺−𝑉𝑇) 𝑉𝐷(1+𝜆 𝑉𝐷) [1+( 𝑉𝐷 𝛼𝑆 (𝑉𝐺−𝑉𝑇) ) 𝑚 ] 1 𝑚 (5) This mobility model is related to the carrier conduction mechanism of the above mentioned TFTs, where a has been related to specific characteristics of the semiconductor material and has been satisfactorily used for different kinds of TFTs [21-24]. In the above threshold regime, the model parameters are: µ0 or µ1, VT, a, Vaa, R, S, m and . R is the total series resistance, S is the saturation parameter, while m and  are the knee of the output characteristic and the channel length modulation parameter, respectively. They are extracted as indicated in [21]. In the subthreshold region near VT, the current is described by an empirical expression neglecting R, where VT → VFB; a→ b and Vaa→ Vbb. 𝐼𝐷𝑠𝑢𝑏 = 𝑊 𝐿 𝐶𝑖 𝜇0 ( 𝑉𝐺−𝑉𝐹𝐵 𝑉𝑏𝑏 ) 𝛾𝑏 (𝑉𝐺 − 𝑉𝐹𝐵) 𝑉𝐷 (6) In the deep subthreshold regime, when the current transport mechanism is diffusion and the current has an exponential dependence, the following equation is used: 𝐼𝐷𝑑𝑒𝑒𝑝𝑠𝑢𝑏 = 𝐼𝐷𝑠𝑢𝑏(𝑉𝐺 = 𝑉1𝐴)𝑒𝑥𝑝 [ 2.3 𝑆 (𝑉𝐺 − 𝑉1𝐴)] (7) The model parameters in the sub-threshold regime are S, VFB, Vbb, b. Current continuity between deep sub-threshold and sub-threshold is obtained by using the tanh function and parameters V1A, V1, Q1 and between subthreshold and above threshold using parameters V2 and Q2, considering (5), (6) and (7). The total subthreshold current is equal to: 𝐼𝐷𝑠𝑢𝑏𝑡𝑜𝑡𝑎𝑙 = |𝐼𝐷𝑑𝑒𝑒𝑝𝑠𝑢𝑏|[1 − 𝑡𝑎𝑛ℎ[(𝑉𝐹𝐵 + 𝑉1)𝑄1]] + |𝐼𝐷𝑑𝑒𝑒𝑝|[1 − 𝑡𝑎𝑛ℎ[(𝑉𝐹𝐵 + 𝑉1)𝑄1]] (8) The total current expression is: 𝐼𝐷𝑆 = [(𝐼𝑜 + 𝐼𝐷𝑠𝑢𝑏𝑡𝑜𝑡𝑎𝑙 ) [1−𝑡𝑎𝑛ℎ[(𝑉𝐺𝑆−(𝑉𝑇+𝑉2))𝑄2]] 2 + |𝐼𝐷| [1+𝑡𝑎𝑛ℎ[(𝑉𝐺𝑆−(𝑉𝑇+𝑉2))𝑄2]] 2 ] (9) where V1A, V1, Q1, V2 and Q2 are adjusting parameters. Determing the Characteristics of the Localized Density of States Distribution Present in MoS2 2D FETs 613 The obtained values for these adjusting parameters for T1 are: V1A=-0.14 V; V1=-0.14 V; Q1=20; V2=1.13 V and Q2=3.76. For T2, V1A=-0.13 V; V1=-0.17 V; Q1=14.5; V2=1.13 V and Q2=27. 0 1 2 3 4 5 0 5 10 15 20 25 30 measured L= 5 m modeled measured L= 0.1 m modeled I D [  A ] V G [V] Transfer V D = 0.2 V a) 0 1 2 3 4 510 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 measured L= 5 m modeled measured L= 0.1 m modeled I D [  A ] V G [V] Transfer V D = 0.2 V b) Fig. 2 Modelled and measured linear transfer characteristic for T1 and T2 in: a) linear scale and b) semilog scale Fig. 2 and Fig. 3 show the measured and modelled linear transfer and output characteristics for devices T1 and T2, where an excellent agreement is observed. For device T1, the value of the field effect mobility at 5 V was µFE= 21.1 cm2/Vs and for T2 µFE= 3 cm2/Vs. From the modelled transfer characteristics, using the procedure in [24], a characteristic energy for the localized DOS distribution in the semiconductor layer of 0.0036 eV was obtained for T1 and 0.034 eV for T2, corresponding to a characteristic energy EtA of 0.034 eV. The values of field effect mobility, total resistance and DOS characteristic energy obtained from modelling, will be further used in simulations as initial values. 0 1 2 3 4 5 0 100 200 300 measured L= 5 m modeled measured L= 0.1 m modeled I D [  A ] V D [V] V G = 6 V Fig. 3 Measured and modelled output characteristic for devices T1 and T2, at VG= 6 V 614 A. BROCHE, A. CERDEIRA, B. IÑIGUEZ, M. ESTRADA 3. SIMULATION OF 2D TRANSISTORS To further analyse the presence and characteristics of a localized DOS, in the bandgap of the MoS2 layer, we used simulation tools, in this case simulator Atlas from Silvaco [25]. The cross section of the simulated devices is shown in Fig. 4a. The thickness of the semiconductor layer was 0.9 nm. Fig. 4b shows a zoom of the semiconductor layer in Fig. 3a, where the channel length L of device T1 was 5 m and of T2 was 100 nm. Other structure device parameters are shown in Table 1. The semiconductor band gap, EG, for the MoS2 monolayer was 1.86 eV, which is a typical value for the direct bandgap present in monolayers, [26]. The charge concentration considered was 1.5x1018 cm-3 [27], NC and NV are the density of states at the bottom of the conduction band and top of the valence band, respectively and Qf is the interface charge density, see Table 2. Table 2 Material parameters used in simulations EG [eV] [26] NB [cm3] [27] Affinity [eV] [30] ks [28] Metal WF [eV] Nc [cm-3] Nv [cm-3] Qf [cm-2] Si P++ NB [cm-3] 1.84 1.5x1018 4.2 2.8 4.3 5x1018 5x1018 3x1011 1x1018 Table 3 Values of the FET devices obtained from simulations: mobility µFE, series resistance R, density of acceptor tail states NtA and characteristic energy of acceptor tail states, EtA. µFE [cm2/Vs] R [Ω] NtA [cm-3] EtA [eV] Device T1 23 250 4.5x1020 0.034 Device T2 5.5 250 4.5x1020 0.034 Fig. 4 a) Cross section of the T2 simulated structure, with scales in m; b) Zoom of the semiconductor layer, where L is the channel length of each of the analysed devices Determing the Characteristics of the Localized Density of States Distribution Present in MoS2 2D FETs 615 Table 3 shows the values of the field effect mobility µFE, interface fixed charge, total resistance, density of tail acceptors in the bandgap DOS distribution and its characteristic energy with which good adjustment between simulated and measured I-V curves in the above threshold region is obtained, see Fig. 5a and b. In the subthreshold region, especially in deep subthreshold, the adjustment was not as good, which can be due to external effects that become more important as the channel length is reduced and were not considered in the simulations. The value for the density of tail acceptors in the bandgap DOS obtained is equal to NtA =4.5x1020 cm-3. Fig. 5 Measured and simulated linear transfer curves for devices T1 and T2: a) in linear scale and b) in semilog scale 4. ANALYSIS OF RESULTS Using modelling and simulation, it was confirmed the presence of a localized tail distribution of states (DOS) in the semiconductor gap, which can be associated with defects present in the MoS2 monolayer. The presence of defects in these monolayers or several layer films, has been observed previously by physical characterization of the layers and has been associated to the presence of grains, grain boundaries, and several types of defects, even though the deposition method should provide high quality crystalline layers [15-20]. It was also possible to determine the characteristic temperature and density of the tail acceptor states present in these devices, which has not been reported before. For the devices with different channel lengths, the simulations were done, using the same material parameters shown in Table 2. As can be seen from Table 3, the characteristics of the tail DOS for devices T1 and T2 are the same, as was to be expected since both types of devices were fabricated at the same time, varying only the channel length in the layout. It is important to remark that in the analysed devices, the main transport mechanism observed is VRH hopping, in which we agree with previous reports. 5. CONCLUSIONS The agreement between measured and simulated transfer characteristics in the analysed devices can be obtained, only if the simulation is done including the presence of a localized DOS distribution in the semiconductor MoS2 layer. This result indicates that the deposited MoS2 monolayers in these FETs present defects giving rise to a predominant hopping transport mechanism. Previously, transfer and output characteristics for both devices, T1 a) b) 616 A. BROCHE, A. CERDEIRA, B. IÑIGUEZ, M. ESTRADA and T2, were modelled with good agreement between modelled and experimental curves, using an expression for mobility that depends as a potential law with the gate voltage. This dependence is normally observed in amorphous or polycrystalline devices, where the hopping transport mechanism is predominant. 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