Design Methologies for Integrated Inductor-Based Soft-Switching DC DC Converters Design Methologies for Integrated Inductor-Based Soft-Switching DC-DC Converters Vitor Costa Pedro M. Santos Beatriz V. Borges Inst. de Telec., Lisboa, Portugal. Área Dep. de Eng. Electrónica e Telec. e de Comp., ISEL, Lisboa, Portugal. vsc@cedet.isel.ipl.pt Inst. de Telec., Lisboa, Portugal. Academia Militar, Lisboa, Portugal pedro.santos@lx.it.pt Inst. de Telec., Lisboa, Portugal. Dep. de Eng. Electrónica e de Comp., IST, Lisboa, Portugal. mbvb@lx.it.pt Keywords: High switching frequency, Quasi-Resonant topologies, CMOS integrated circuits, Power management. Abstract: This paper presents a study on resonant converter topologies targeted for CMOS integration. Design methodologies to optimize efficiency for the integration of Quasi-Resonant and Quasi-Square-Wave converters are proposed. A power loss model is used to optimize the design parameters of the power stage, including the driver circuits, and also to conclude about CMOS technology limitations. Based on this discussion, and taking as reference a 0.35μm CMOS process, two converters are designed to validate the proposal: a Quasi Resonant boost converter operating at 100MHz and a Quasi-Square-Wave buck converter operating at 70MHz. Simulation results confirm the feasibility of these topologies for monolithic integration. 1 INTRODUCTION Power management circuits for battery powered portable electronic equipment are being more demand, imposing the research on very efficient solutions. In some of these equipments the difference between the battery and the circuit voltage are significant. For this kind of applications the use of inductor-based switching topologies in the conception of integrated DC-DC converters in CMOS technology have inherent advantages, in order to achieve good performances and compactness, at low cost. The main design specifications for an inductor-based CMOS DC-DC converter are usually the ratio between the input and output voltages, the output power or load current, and the output voltage ripple. Nevertheless, additional variables such as the switching frequency and the inductor current ripple have also to be considered, since they have a direct impact on Silicon footprint, efficiency and system Electromagnetic Interference (EMI). The fully integration of an inductor-based DC-DC converter in CMOS technology brings new challenges. The inductor and capacitance integration are restricted to low values, when compared with the discrete implementation, due to the available Silicon area. The low value integrated capacitors present reasonable behaviour and are normally used on mixed-signal. However, integrated inductors on standard CMOS process are only available for a few nH and specifically target for RF-CMOS applications. Many authors have presented solutions with the objective of fully integrate switch-mode DC-DC buck converters [1-11]. Distinct solutions have been proposed. Some of the solutions are based on Discontinuous Conduction Mode (DCM) operation, in order to reduce the filter inductor to an acceptable value for CMOS, below 20 nH [7,9]. However, DCM operation implies overstress on power transistors for the same output load current. Other solutions make use of the stacked chip concept to perform a System in a Package (SiP) [8], which are not cost effective [1, 9]. Finally another approach is supported on the research of new design methodologies that leads to full integration, maintaining specifications competitive when compared with other hybrid and costly solutions [1-6]. It is well known that the physical dimensions and consequently the parasitic impedances of the filter passive components are greatly reduced as the converter switching frequency increases. In that case, the increase in the switching frequency could become the key parameter for full integration. For very high switching frequency the power transistors i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 http://journals.isel.pt/index.php/IAJETC and respective driver power losses dominate the losses on the converter [2], mainly due to the increase of the switching losses, turning the design of the power stage even more relevant [1-6, 12]. Although, the study of optimization methods on the design of the converters power stage [1-6, 12], all the solutions presented are based on hard-switching. So, the study of alternative solutions that could present lower switching losses maintaining high efficiency at high switching frequency is a major challenge. Among the Power Electronics DC-DC converters circuit topologies, the soft-switching topologies [13, 14, 15] are distinguished by their efficiency and low Electromagnetic Interference (EMI). Thus, the use of soft switching techniques appears attractive to minimize noise and switching losses [16]. The objective of this paper is to present design methods based on the analytical loss model of the power stage described on [12] for soft-switching topologies. On section 2 the ZVS (zero voltage switch) Quasi Resonant converters are introduced discussing the necessity of defining a design procedure tailored for CMOS integration. A design procedure based on the theoretical operation for a boost converter is presented, which contemplates the power transistors and respective driver circuit optimization. Section 3 introduces the ZVS Quasi Square Wave converters. A design method for the buck topology with power transistors and respective driver circuit optimization is also presented. Several simulation results based on a standard 0.35 μm CMOS process are shown in section 4 for the two types of resonant switching converters, in order to verify and validate the viability of the theoretical approach. Conclusions are presented in section 5. 2 QUASI-RESONANT CONVERTERS Quasi-Resonant Converters are obtained from conventional PWM (Pulse Width Modulation) converters by using resonant switches. The difference between these switches and the conventional PWM switches is the inclusion of an inductor and a capacitor, as shown in Figure 1, in order to allow ZCS (zero current switch) (a), or ZVS (zero voltage switch) (b). As a consequence, theoretically, switching frequency can be increased with reduced switching losses and increased power density for integration purposes. a) b) Fig. 1. a) Buck ZCS QR converter; b) Boost ZVS QR converter. For monolithic integration in CMOS technology, the use of intrinsic MOSFET transistor capacitance as the resonant capacitor is a possibility. However, this is only valid for ZVS topologies. In fact, MOSFET parasitic capacitances distribution in ZCS converters, do not match with the specific resonant capacitor C0, as can be confirmed in Figure 1 a). Furthermore, maximum current on the active switch is, at least, the double of the maximum current on a PWM equivalent converter [17]. These aspects reinforce the use of ZVS topologies for CMOS integration. For these reasons only the ZVS topologies are considered in this work. 2.1 Boost Quasi-Resonant Converter Theoretical Operation A detailed steady state analysis of the ZVS-QR buck topology is presented in [18]. Based on that analysis, a design procedure for discrete ZVS-QR buck converter is developed in [15]. This study can be extended for the boost topology only with some modifications. The resonant circuit, composed by L0 and C0, dominates the operation and mainly define the converter characteristics. For better comprehension consider the following parameters of the converter: characteristic impedance Z0, the resonant frequency f0, the normalized load resistance Q and the conversion ratio M: 0 0 0 C L Z = (1.a) 00 0 2 1 CL f ⋅⋅⋅ = π (1.b) 0 Z R Q L= (1.c) I O V V M = (1.d) where RL is the load resistance. RL Vo S2 LL0 C0 S1 C0 Control fs CVs Control fs Control fs C0 C RL Vo Vs L L0 S2 S1 V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC The conversion ratio of the ZVS-QR boost converter can be obtained, as in the case of the ZVS-QR buck converter in [18]: ( )MQ f f M s ,,φ 2 1 0 α π ⋅ ⋅⋅ = (2.a) with: ( ) ( )ααα cos1 2 ,,φ −⋅+ ⋅ += Q M M Q MQ (2.b) where:       += M Q arcsinπα (2.c) To describe M as function of the control variable, the switching frequency fs, it is necessary to use a numerical procedure. However it is possible a closed form solution, with some rearrangement of equation (2.a): ( ) ( )MQ M f f s ,,φ 12 0 α π −⋅⋅ = (3) The regulation characteristic obtained from equation (3) shows that the load variation implies adjustments on the control variable to regulate the output voltage. This means that not only is necessary adjustments on control variable when the converter ratio varies but also when the load value changes. These changes could compromise the critical condition that guaranties zero-voltage switching, QM ≥ . Designing ZVS-QR converters requires the design of the resonant circuit, the filter components and the power switches that includes the power MOSFET and the respective drivers. The design of the filter components is similar to that of the PWM converters, considering the minimum switching frequency. 2.2 Design Procedure for Boost Quasi-Resonant Converter Typically, the design specifications for a CMOS dc- dc converter include: output voltage, VO; input voltage range, minI V to maxI V ; the load resistance range, minL R to maxL R ; maximum switching frequency, maxS f . From the design specifications, the maximum and minimum value for the conversion ratio is given by: max min I O V V M = (4.a) min max I O V V M = (4.b) Considering the input voltage and load range the worst condition that could compromise the zero- voltage switching occurs for the minimum conversion ratio, Mmin, and maximum normalized load, Qmax, defining a boundary condition described by equation (5). min 0 0 maxmax max M R Z Z R V V LL I O ≥⇔≥ (5) This situation will correspond to the maximum switching frequency, maxS f , given the minimum value for the characteristic impedance. For the definition of the input voltage and load range the maximum voltage value that the NMOS MOSFET, acting as active switch, supports, must be taken into account. This aspect is fundamental when designing DC-DC converters in CMOS technology. The relation between the maximum value and the input voltage and load ranges will be given by:         ⋅+⋅= min max max min max1 L L ODSNMOS R R M M VV (6) Equation (6) shows that even for fixed load and input voltage the maximum voltage on the active switch is twice the maximum voltage at the converter output. This will represent a problem if the output voltage is near the maximum CMOS process voltage, or for high load variations, especially if the switching frequency rises to tens or even hundred of MHz (although there is the possibility of producing high-voltage CMOS compatible transistors [19], these transistors operate at lower frequencies). The maximum current for the same transistor, in the worst case, can be obtained considering the maximum conversion ratio and the maximum load current. maxmaxmax max OLDNMOS IMII ⋅== (7) For the PMOS MOSFET, the maximum voltage stress and the maximum current stress will occur for πα = . V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC ODSPMOS VV −≅max (8.a) maxmax max2 ODPMOS IMI ⋅⋅= (8.b) Considering the situation of maximum switching frequency, corresponding to maxII VV = and maxLL RR = , and that Z0 assume the minimum value given by equation (5), equation (3) will be rewritten as: ( )      −++⋅ ⋅ = αα π cos1 2 1 2 min 0 max M f f S (9) In the situation of boundary condition 2 3 max π αα ⋅ == equation (9) simplifies to: ( ) minmin0 1 13 4 max MMf f S ≅ +⋅⋅ ⋅ = π π (10) The minimum switching frequency will be achieved when minII VV = and minLL RR = . In this way, equation (3) assumes a new form: ( )         −++ = αα π cos1 2 2 min max min max min max 0 min max max m n min MR MR MR MR M f f L L L L S (11.a) with:         ⋅ ⋅ += max min min max minarcsen MR MR L L πα (11.b) For CMOS integration the maximum switching frequency will assume particular importance, due to CMOS process limitations on frequency and converter efficiency optimization. In this way the maximum switching frequency must be chosen to meet the above requirements and will depend on the CMOS process in use. Resonant frequency, 0f , will be obtained after using equation (10). With the value of the resonant frequency and the characteristic impedance imposed by the boundary condition the resonant circuit components are given by the follow equations: 0 0 0 2 f Z L ⋅⋅ = π (12.a) 00 0 2 1 Zf C ⋅⋅⋅ = π (12.b) An extension of the design method used for hard- switching converters for the design of the power switches and respective driver circuits, presented on [12], can be used for ZVS-QR converters. C G S P 2 P C GD P2P C G S N 2 P CGD N2P C G B N 2 P C G B P 2 P C D B N 2 P C D B P 2 P P 2P N2P C G S P 2 N CGD P2N C G S N 2 N CGD N2N C G B N 2 N C G B P 2 N C D B N 2 N C D B P 2 N P2N N2N C G S P 3 P C GD P3P C G S N 3 P CGD N3P C G B N 3 P C G B P 3 P C D B N 3 P C D B P 3 P P 3P N3P N1 C D B N 1 C G S N 1 C G B N 1 C G D N 1 C D B P 1 C G S P 1 C G B P 1 P 1 C G D P 1 R O N P 1 R O N N 1 C G S P 3 N CGD P3N C G S N 3 N CGD N3N C G B N 3 N C G B P 3 N C D B N 3 N C D B P 3 N P3N N3N Switching Frequency Variation Control VO VO VO VO VO VO Vgn Vgn Vgn VgnVgp Vgp Vgp Vgp Lf Cf L o a d PMOS gate-driver NMOS gate-driver WP3P= b(b+1)WP1 ap 2 WP3N= b(b+1)WN1 an 2 WN3N= (b+1)WN1 an 2 WN3P= (b+1)WP1 ap 2 WP2P= bWP1 ap WP2N= bWN1 an WN2N= WN1 an WN2P= WP1 ap VI L0 C0ext Fig. 2. ZVS-QR Boost converter model including parasitic impedances and transistor sizes. V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC 2.3 Power Stage Loss Model The power loss model is obtained considering the proposed method for buck hard-switching DC-DC converters on [12]. This method could be extended, with a few modifications on the power MOSFET and the respective drivers design model, for buck ZVS-QR dc-dc converters. A boost ZVS-QR converter model that includes the parasitic impedances is shown in Figure 2. The losses of the driver circuit of the PMOS power device, P1, shown on Figure 2, are the same as for the buck hard-switching dc-dc converters, [12]. For the PMOS power transistor the energy associated to the switching losses per unit will be slightly different and given by: ( ) ( )2 0001 gpOPMOSgdPMOSgsPMOSgbP VVCCCE −⋅++= (13) Considering the contributions from the driver circuit and the power losses from the PMOS power transistor, the total power loss associated to P1 is obtained from: ShingTOTALswitcPPrmsPMOS P PMOS TOTALP fEWi W R P ⋅⋅+⋅= 11 2 1 0 1 (14.a) with: sPMOSdriverPhingTOTALswitcP EEE += 11 (14.b) Where PMOSR0 is the PMOS on resistance per unit length, WP1 is the P1 width, fs the switching frequency and rmsPMOSI the PMOS rms current. For the NMOS transistor, N1, and the respective driver circuit, similar equations are obtained: ShingTOTALswitcNNrmsNMOS N NMOS TOTALN fEWi W R P ⋅⋅+⋅= 11 2 1 0 1 (15.a) with: sNMOSdriverNhingTOTALswitcN EEE += 11 (15.b) where: ( ) 2 0001 gnNMOSgdNMOSgsNMOSgbN VCCCE ⋅++= (15.c) From (14) and (15) it can be concluded that the conduction losses are proportional to the width of power MOSFET. In this way it is possible to optimize the losses on the power transistors and respective drivers, as in [12] for hard-switch converters. For the definition of the tapering factor, tf, it has to be consider the losses in the driver circuits, as in [12] for hard-switch converters, remaining the functional behaviour of the converter. So, a different solution based on [3] was used, where tf is defined as five to ten times less than the charge of the resonant capacitor, C0, corresponding to the first operating interval of ZVS-QR boost converter, the short time interval. 3 QUASI-SQUARE-WAVE CONVERTERS As in the case of the QR Converters, the ZVS-QSW and ZCS-QSW converters are also obtained from conventional PWM (Pulse Width Modulation) with some additional reactive components, with a different circuit topology. ZVS-QSW converters present lower voltage and higher current stress on the switching devices. On the other hand ZCS-QSW converters have lower current and higher voltage stress [20]. The ZVS- QSW topologies present the advantage of the addition of only one capacitor, when compared with the QR or ZCS-QSW topologies, because theoretically the additional inductor can be placed in parallel with the filter inductor. Thus, ZVS-QSW topologies appear as an alternative to the use of high-voltage transistors in ZVS-QR topologies. Another advantage is that the parasitic capacitors associated to the two power transistors are in parallel and contribute both to the resonant capacitor. However, it is necessary to take into account some drawbacks: the higher variation of the inductor current, which leads to an increase of the Electromagnetic Interference (EMI) when compared with the Quasi-Resonant topologies. To obtain a QSW converter it is necessary to manipulate the low-frequency storage elements in the correspondent PWM topology, followed by the insertion of resonant tank elements. Certain PWM converters cannot be transformed into their corresponding ZVS-QSW or ZCS-QSW topologies, unless new low frequency storage elements are added to the original PWM converter (e.g. the ZCS buck converter) [20]. This solution is only attractive for the topologies that do not need the additional low-frequency elements, as the ZVS buck converter, presented in Figure 3. V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC V S V O RL C L f S control C 0 S 1 S2 Fig. 3. Buck ZVS-QSW converter. In this converter the output filter inductor is also used as the resonant inductor. Therefore, this solution appears more attractive then the correspondent QR topology, presented in Figure 1. b), since the resonant inductor is not present. 3.1 Buck Quasi-Square-Wave Converter Theoretical Operation A detailed steady state analysis of the buck ZVS-QSW converter theoretical operation is presented in [20]. Using this steady state analysis and performing an energy balance for one operation period, considering no losses, it is possible to obtain a set of five equations which resolution is not trivial. In order to solve this problem, a semi closed method to obtain the conversion ratio for the design of a buck ZVS-QSW converter was developed in [21]. Using the result obtained in [21] the frequency conversion ratio is given by: ( )      −⋅−⋅⋅ −⋅⋅⋅ = 12 )1(4 2 2 2 2 2 0 M I I Q M Q MM f f L M s π (16) Assuming that M is known and that the parameter Q is function of the load and of L0, the only unknown variable is IM (maximum current in the inductor). The ratio between the maximum and average currents in the inductor, LMI IIL /=α , results from the solution of (17): 0 23 =+⋅+⋅+⋅ dcba LLL III ααα (17) where: ( )MQ a −⋅ −= 12 1 (17.a) ( )MQ M Q b −⋅ += 1 1 (17.b) ( ) ( )MM QM M MM M c −⋅⋅ ⋅−⋅ +−⋅ ⋅ − +      − = 12 12 12 1 11 arccos 2 (17.c) QMd ⋅= (17.d) From equation (17) three solutions are obtained for LI α , but only one is in agreement with the normal behaviour of the converter. Substituting in (16) the valid LI α it is possible to obtain the conversion ratio, M, as function of the normalized switching frequency for different values of the normalized load, Q. As in the ZVS-QR boost converter the load variation implies adjustments on the control variable to regulate the converter output voltage. This variation forces a critical condition to guarantee the zero voltage switching in the ZVS-QSW converter. In this case, independently of the normalized load, 5.0≥M . Nevertheless, a design procedure is needed to design a ZVS-QSW buck converter in CMOS technology. The zero voltage switching critical condition implies the limitation of these converters to applications where the conversion ratio is above 0.5. Designing ZVS-QSW converters have the same requirements as in the ZVS-QR converters. It is necessary to design the resonant circuit, the filter components and the power switches that include the power MOSFET and the respective drivers. Because of that a new design procedure is developed for CMOS ZVS-QSW converters in the next section. 3.2 Design Procedure for Buck Quasi-Square-Wave Converter Some authors have proposed design methods for ZVS-QSW converters, [22]. However these methods are not appropriated for CMOS integration. A new proposal was made in [21] but without the design procedure for the power stage. In this way a more detailed and improved method is proposed in this paper. The CMOS monolithic integration of ZVS-QSW converter implies a careful attention over the definition of circuit parameters. As a matter of fact the linear approximation made to obtain equation (16), is only valid if the normalized switching frequency is low [21]. This implies that Q should have the smallest value as possible (from equation (16)). Considering all the dependencies of Q, including the switching frequency, the load and V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC characteristic impedance Z0, and taking into account the parameters of the CMOS process, the following design method is proposed: 1. Define the normalized load, Q, that with the conversion relation, M, of the converter to be designed, corresponds to a small ratio between the switching frequency and the resonant frequency. 2. With Q defined, obtain the characteristic impedance, Z0, considering the maximum load resistance, maxL R , corresponding to the boundary condition. Obtain the ratio between IM and IL using equation (17). Determine the ratio between the maximum switching frequency, maxS f , and the resonant frequency using equation (16). 3. Design the power transistors and associated drivers using an extension of the method used in [12], function of the load current, IO, and the maximum switching frequency, maxS f , which is defined considering the compromise between the occupied area and the converter efficiency, taking into account the limitations inherent to the specific CMOS process. Obtain the resonant frequency with the information of step 2. 4. Obtain the intrinsic parasitic capacitors of the power transistors that contribute to the resonant capacitor, C0. The sum of these capacitances must be smaller than the resonant capacitor determined after steps 2 and 3. If not, return to step 1 and relax the specification of Q. With this method it is possible to guarantee a normal behaviour of the converter in the worst case, defining as in the case of the ZVS-QR converters, ranges of variation for the input voltage and output load. After the definition of the maximum normalized load, Qmax, the characteristic impedance could be obtained by: max 0 max Q R Z L = (18) Using equations (16) and (17) and considering the situation of Mmin, it is possible to obtain the values corresponding to the situation of maximum switching frequency, the worst condition to validate the restriction on the ratio between the switching and resonant frequencies. Using the same equations and making maxMM = and 0/min ZRQ L= it is possible to obtain the relation between the minimum switching and resonant frequencies, defining in this way the operating interval of the converter, as function of the ranges of the input voltage and of the load. In the ZVS-QSW buck converter the filter inductor is shunted by the resonant inductor. So, the design of the filter components is reduced to the design of the filter capacitor. The filter capacitor value is obtained in a similar way as for the PWM converters considering the minimal switching frequency operation and assuming a ripple current on the inductor given by half of IM: 2 M L I i ≅∆ (19) The efficiency analysis of the converter is measured considering the situation of maximum switching frequency (with Qmax and Mmin), corresponding to the worst case for dynamical losses on the power stage. 3.3 Power Stage Loss Model The power losses model of the power transistors and respective driver circuits is similar to the power loss model obtained for the ZVS-QR boost converter. The losses on the ZVS-QSW buck converter are characterized in the same way as for the ZVS-QR boost converter. The parasitic capacitances considered are the same because of the zero voltage switching. In this way, the equations from (13) to (15) are valid and can be applied. For the definition of the tapering factor, tf, the solution adopted is the same as in de ZVS-QR boost converter. 4 DESIGN PROCEDURES VALIDATION This section presents simulation results of a ZVS-QR boost converter and a ZVS-QSW buck converter that validates the design procedures proposed in this work. The ZVS-QR boost converter was design for the following specifications: [ ]V32.108.1 L=IV , VO = 3.3V, [ ]mA109L=OI , LL Ii ⋅=∆ 1.0 and ripple output voltage below 1%. Taken as reference a maximum theoretical efficiency of 80% the maximum switching frequency for the CMOS V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC process is 100MHz. With that value and using the design methodology exposed in section 2, the parameters obtained for the converter are: L0 = 90nH, C0 = 4.18pF, Lf = 2.9µ H, Cf = 1.9nF. The optimized transistors dimensions are WNMOS = 339.6µ m, WPMOS = 552.9µ m with LNMOS = LPMOS = 1µ m. The resonant capacitor will be formed by a NMOS parasitic capacitor and an additional shunt capacitor. Fig. 4. Transient Analysis detailed Waveforms of output voltage (vout), inductors currents (IL and IL0), power transistors control signals (vg_nmos and vg_pmos) and resonant capacitor voltage (vc0) of the boost QR converter. Output voltage full transient response waveform. The waveforms presented in Figure 4 shows some drawbacks on the use of ZVS-QR converters for integration purpose. The current in the resonant inductor and the voltage in the resonant capacitor oscillate in the last interval of the switching period. The parasitic resonance results from the accumulated energy in the PMOS parasitic capacitance, Cgd, when acting as the switching transistor. The accumulated energy is injected in a resonant circuit formed by the resonant inductor, L0, and the capacitor resulting from the sum of Cgd with Cdb in the PMOS power transistor. This resonance will be described by the following equations: ( ) ( )( ) LL Itt Z V ti P +−⋅⋅= 30 0 sen 0 ωσ (20.a) ( )( ) OC VttVv P −−⋅⋅= 30cos ωσ (20.b) where σ V represents the Cgd accumulated energy resultant voltage, PC V represents the voltage in the PMOS total parasitic capacitance, the sum of Cgd with Cdb, and P Z 0 represents the characteristic impedance of the parasitic resonance circuit. This parasitic resonance causes a resonant voltage on the PMOS drain that presents a high voltage stress, not supported by the CMOS process. This imposes the use of a high voltage PMOS transistor. The other solution could be the use of a diode in the PMOS place, like in the discrete implementation, but it will lead to less efficiency. This will be a significant drawback in the use of ZVS-QR topologies for CMOS integration. Using the section 3 design procedure, a ZVS-QSW buck converter was designed with the following characteristics: [ ]V2.58.4 L=IV , V3.3=OV , mA30=OI , OO Vv ⋅=∆ 05.0 , L0 = 249nH, C0 = 1.3pF, Cf = 990pF, MHz70 max =Sf . The optimized transistors dimensions were WNMOS = 238.1µ m, WPMOS = 653.9µ m with LNMOS = LPMOS = 1µ m. The waveforms presented in Figure 5 are in good agreement with the expected results. After the transient, the converter tends to stabilize at the desired values for output voltage and average inductor current. Fig. 5. Transient Analysis detailed Waveforms of inductor current, L0, output voltage, vo and PMOS and NMOS control signals. Output voltage full transient response waveform. The theoretically efficiency, considering only the losses of the power transistors, is approximately 80%. The value obtained for the efficiency in the simulated circuit was about 7% less. The difference obtained is mostly caused by the overlap conduction on the inverters of the power transistors driver circuits. 5 CONCLUSIONS Two design procedures for the implementation of resonant switching converters in CMOS technology are introduced. A ZVS-QR boost converter and a ZVS-QSW buck converter were conceived using the proposed design methods. The results obtained show a validation of the proposed design methodologies. Some drawbacks for the implementation of the ZVS- QR converters in CMOS are revealed for the initial assumptions considered. The use of high-voltage PMOS transistors is proposed to solve these V. Costa et al. | i-ETC - CETC2011 Issue, Vol. 2, n. 1 (2013) ID-17 i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers http://journals.isel.pt/index.php/IAJETC drawbacks. Nevertheless the parasitic resonance could cause a higher EMI. The results obtained from the ZVS-QSW buck converter encourage this solution. The introduction of non-overlap circuits in the last inverters of the inverters chain of the power transistors driver circuits could reduce the switching losses. The parasitic resonance in the CMOS integrated ZVS-QR converter reduce the advantage of lower EMI when compared with the CMOS integrated ZVS-QSW converter. In this context the utilization of CMOS integrated ZVS-QR converters will be conditioning to the study of solutions to reduce the parasitic resonance. REFERENCES [1] Volkan Kursun, Silva G. Narendra, Vivek K. De and Eby G. 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