Transactions Template JOURNAL OF ENGINEERING RESEARCH AND TECHNOLOGY, VOLUME 1, ISSUE 4, DECEMBER 2014 103 Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation Dr.P.Usha Rani R.M.D.Engineering College, Chennai, pusharani71@yahoo.com Abstract – The Dynamic Voltage Restorer (DVR) provides an advanced solution for voltage sag/swell problems. The voltage-restoration process involves real-power injection into the distribution system. The Interline DVR (IDVR) proposed in this paper provides a way to compensate the voltage sag/swell caused in a feeder. The IDVR consists of several DVRs connected to different distribution feeders in the power system sharing common energy storage, where one DVR in the IDVR system works in voltage-sag/swell compensation mode while the other DVR in the IDVR system operate in power-flow control mode. The modelling and simulation of single phase IDVR system using Sinusoidal Pulse Width Modulation (SPWM) technique for voltage sag and swell conditions and three phase IDVR using Space Vector Pulse width modulation (SVPWM) technique for voltage sag condition are presented. Closed loop control for voltage sag and swell for a simple IDVR systems are modeled and simulated using MATLAB software. The sim- ulation results are presented to demonstrate the effectiveness of the proposed IDVR system. . Index Terms— Interline Dynamic Voltage Restorer (IDVR), Interline Power Flow Controller (IPFC), Sinusoidal Pulse width modulation (SPWM), Space Vector Pulse width modulation (SVPWM), Total Har- monic Distortion (THD). I INTRODUCTION The need of the electrical power is increasing and simultane- ously the problems while transmitting the power through the distribution system are also increasing. Voltage fluctuations are considered as one of the most severe power quality dis- turbances to be dealt with. Even a short-duration voltage fluc- tuation could cause a malfunction or a failure of a continuous process. There are several types of voltage fluctuation that can cause the systems to malfunction, including surges and spikes, sag, swell, harmonic distortions, and momentary dis- ruptions. Among them, voltage sag and swell are the major power-quality problems. Voltage swell is the sudden increase of voltage to bout more than 110% amplitude of the supply voltage, whereas the voltage sag is the sudden decrease of voltage ton about 90% amplitude of supply voltage. This is caused due to the sudden reduction or addition of the load across that particular feeder. This change of voltage is com- pensated by injecting the voltage in series with the supply from another feeder at the time of disturbances using DVR. This IDVR system is presently one of the most cost-effective and a highly efficient method to mitigate voltage sag/swell. The concept of Interline Dynamic Voltage Restorer (IDVR) where two or more voltage restorers are connected such that they share a common DC-link is similar to the In- terline Power Flow Controller (IPFC) concept. In this paper, a two-line IDVR system is explained which employs two DVRs, connected to a common DC-link, is connected to two different feeders originating from two grid substations, and could be of the same or different voltage level. When one of the DVRs compensates for voltage swell/sag produced, the other DVR in IDVR system operates in power-flow control mode. DVR principles and voltage restoration methods at the point of common coupling are presented. The problem of voltage sags and swells and its severe impact on sensitive loads are described [1]. Voltage swell and overvoltage com- pensation problems in a diode bridge rectifier supported transformer-less coupled DVR, are discussed. The simulation and experimental results for unbalanced voltage swell com- pensation are given [2]. The performance of a DVR in miti- gating voltage sags/ swells is demonstrated with the help of MATLAB. The DVR handles both balanced and unbalanced situations [3]. The modeling and simulation of IDVR is presented in paper [4] and [6]. Paper [5] proposed a new topology based on the Z source inverter for the DVR, in order to enhance the voltage restoration property of the device. The modeling as- pects of the DVR working against voltage sags by simulation in the PSCAD/EMTDC have been presented [7]. Modeling Dr.P.Usha Rani/ Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation (2014) 104 and simulation of single phase IDVR using multiple PWM technique is presented [8] and [10].The modeling and simu- lation of single phase Z source impedance based DVR, IDVR using multiple PWM technique is presented [9] and [13]. In this paper, modeling and simulation of single phase IDVR with SPWM technique is used for voltage sag and swell com- pensation. II. PRINCIPLE OF IDVR The IDVR system consists of several DVRs in dif- ferent feeders, sharing a common DC-link. A two-line IDVR system shown in Fig.1 employs two DVRs are connected to two different feeders where one of the DVRs compensates for voltage swell/sag produced, the other DVR in IDVR system operates in power-flow control mode. The common capacitor connected between the two feeders act as the common DC supply. and simulation of single phase IDVR using multiple PWM technique is presented [8] and [10].The modeling and simulation of single phase Z source impedance based DVR, IDVR using multiple PWM technique is presented [9] and [13]. In this paper, modeling and simulation of single phase IDVR with SPWM technique is used for voltage sag and swell compensation. Voltage swell/sag in a transmission system are likely to propagate to larger electrical distance than that in a distri- bution system. Due to these factors, the two feeders of the IDVR system in Fig.1 are considered to be connected to two different grid substations. It is assumed that the voltage dis- tortion in Feeder1 would have a lesser impact on Feeder2. Fig.1 Schematic diagram of an IDVR The upstream generation-transmission system is ap- plied and the two feeders can be considered as two independ- ent sources. These two voltage sources Vs1 and Vs2 are con- nected in series with the line impedances Zl1 and Zl2 which is in-turn connected to the buses B1 and B2 as in Fig. 1. The DVR is connected in series with the feeder and the DVRs across different feeders are connected by a common DC-link. The load across each feeder is connected in series to the DVR, where Vl1 and Vl2 are the voltages across the load. The injection of an appropriate voltage needs a cer- tain amount of real and reactive power which must be sup- plied by the DVR. Supply of real power is met by means of an energy storage facility connected in the DC-link. Large ca- pacitors are used as a source of energy storage in most of the DVRs. Generally, capacitors are used to generate reactive power in an AC power system. However, in a DC system, ca- pacitors can be used to store energy. When the energy is drawn from the energy storage capacitors, the capacitor ter- minal voltage decreases. Hence, large capacitors in the DC- link energy storage are needed to effectively mitigate voltage swell of large depths and long durations. The pulse can be generated using various modulation techniques. In this paper, the pulse for the switch is generated using SPWM. III. MODEL OF IDVR USING SPWM TECH- NIQUE The simulink models of the closed loop controlled IDVR system with the H bridge inverter using SPWM tech- nique for sag and swell conditions are developed and the sim- ulation results are presented. The IDVR system with two back- to-back connected DVR stations was implemented with a closed loop control of inverter switches. Fig.2 shows the sim- ulink model of the closed loop controlled IDVR. The rectifier- inverter system is shown as a subsystem. Fig.2 Simulation Circuit of IDVR v + - v + - v + - Out1 in1 in2 Subsystem2 In1 in1 in2 Conn1 Conn2 Subsystem1 Scope2 i + - Current Measurement 4 ohm 40mH 3ohm 18mH1 3ohm 18mH 350 V 1 2 1 2 200V 10 ohm 100mH 10 ohm 100mH 0.2 to 0.51 0.2 to 0.5 Dr.P.Usha Rani/ Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation ( 2014) 105 The subsystem 1 consists of a full bridge inverter with a filter. Subsystem 2, shows the rectifier output voltage The SPWM control technique is used to reduce the harmonic content in the output voltage. The driving sine pulses for the switches are shown in Fig.3. Fig.4 (a) shows a 32.6 % voltage sag initiated at 300ms and it is kept until 600ms, with a total voltage sag du- ration of 300ms in low voltage feeder 1. Fig.3 (b) and (c) show the voltage injected by the DVR 2 and the compensated load voltage respectively. Due to the presence of the IDVR, the load voltage remains constant throughout the voltage sag period. Fig.5 shows the common DC link voltage waveform. Fig.6 shows the FFT analysis of the closed loop IDVR system for sag. The Total Harmonic Distortion (THD) value is 4.81%. Fig.3 Driving pulses of inverter switches Fig.4 Response of IDVR to a voltage sag Fig.5 Common DC link voltage for sag Fig.6 FFT analysis of IDVR for sag Fig.7 (a) shows a 44.1 % voltage swell initiated at 300ms and it is kept until 600ms, with a total voltage swell duration of 300ms in low voltage feeder 1. Fig.7 (b) and (c) show the voltage injected by the DVR 2 and the compensated load voltage respectively. Due to the presence of the IDVR, the load voltage remains constant throughout the voltage swell period. Fig.8 shows the common DC link voltage wave- form. Fig.9 shows the FFT analysis of the closed loop IDVR system for swell. The Total Harmonic Distortion (THD) value is 0.12%. 0.4 0.405 0.41 0.415 0.42 0.425 0.43 0.435 0.44 0 0.5 1 1.5 2 v o lt a. Gate pulse 1,2 0.4 0.405 0.41 0.415 0.42 0.425 0.43 0.435 0.44 0 0.5 1 1.5 2 Time(sec) v o lt b. Gate pulse 3,4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -200 0 200 v o lt a. uncompensated voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -200 0 200 v o lt b. Injected voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -200 0 200 Time(sec) v o lt c. Compensated voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -2000 -1500 -1000 -500 0 500 1000 Time(sec) v o lt Dr.P.Usha Rani/ Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation (2014) 106 Fig.7 Response of IDVR to a voltage swell Fig.8 Common DC link voltage for swell Fig.9 FFT analysis of IDVR for swell IV. IDVR USING SVPWM TECHNIQUE The proposed IDVR circuit with the Space Vector PWM is shown in Fig.10. Here, the error voltage in the dq- frame is used to calculate the resultant reference voltage and angle α of the space vector eight sector frame work. Table. 1 shows the parameters used for simulation studies. The subsystem 1 consists of feeder 1 and DVR 1 as shown in Fig.12. The DVR 1 consists of an inverter, switch- ing time calculator and switching pulse generator. The sub- system 2 consists of feeder 2 and DVR 2. The DVR 2 has an inverter, switching time calculator and switching pulse gen- erator. Fig. 10 Simulation circuit of three phase IDVR Table. 1 Parameters of the two line IDVR Supply voltage feeder 1 240V Supply voltage feeder 2 707V Source Impedance (0.1+j3.142*e-4)Ω Line impedance (for 100km) (1.6+j0.34)Ω Series transformer turns ratio 1:1 Injection transformer ratio 1:1 DC voltage 260V Fixed Load resistance 40Ω Fixed Load inductance 60mH Filter inductance 10mH Filter capacitance 0.0177µF Line frequency 50Hz Carrier frequency 12003Hz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -200 0 200 v o lt a. uncompensated voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -200 0 200 v o lt b. Injected voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -200 0 200 Time(sec) v o lt c. Compensated voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -1000 -800 -600 -400 -200 0 200 400 600 Time(sec) v o lt s Conn2 Conn1 Subsystem1 Conn2 Conn1 Subsystem DC Voltage Source Dr.P.Usha Rani/ Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation ( 2014) 107 Fig.12 Subsystem 1 of three phase IDVR Fig.13 indicates that 27.42% voltage sag is initiated at 300ms and it is kept until 800ms, with a total voltage sag duration of 500ms in the low voltage feeder 1. Fig.14 (a) and (b) show the voltage injected by the DVR2 and the compen- sated load voltage respectively. Due to the presence of the IDVR, the load voltage remains constant throughout the voltage sag period. Fig.15 shows the FFT analysis of the three phase IDVR with the SVPWM model. The THD of the SVPWM system is found to be 0.08 %. Fig.13 Voltage sag of three phase IDVR Fig.14 Response of three phase IDVR to a voltage sag Fig.15 FFT analysis of the three phase IDVR V. CONCLUSION The modelling and simulation of single phase IDVR system using SPWM technique for sag and swell conditions are presented. The modelling and simulation results of three phase IDVR using space vector PWM technique are also pre- sented. The model of single phase IDVR for 44.1% of the voltage swell and 32.6% of the voltage sag is compensated using closed loop control. The model of three phase IDVR for 27.42% of the voltage sag is compensated using closed loop control. The simulation results indicate that the imple- mented control strategy compensates voltage sags with high accuracy. The results show that the control technique is an improved method for voltage sag and swell compensation. 2 Conn2 1 Conn1 atan2 alpha abc sin_cos dq0 abc_to_dq0 Transformation1 abc sin_cos dq0 abc_to_dq0 Transformation v + - sin cos A 1 + A 1 B 1 + B 1 C 1 + C 1 A 2 + A 2 B 2 + B 2 C 2 + C 2 Vabc A B C a b c V a b c A B C a b c Vabc A B C a b c Vabc A B C a b c A B C A B C A B C A B C A B C A B C A B C A B C N A B C N A B C sector mag alpha alpha1 Tz T1 T2 T0 Switching time Calculator T1 T2 T0 Sector Timing Switching pulse generator Scopee Scoped Scopec Scopeb2 Scopeb1 Scopeb Scopea > PID(s) PID Controller node 0 sqrtu 2 u 2 MAT LAB Function MAT LAB Fcn Gate Port1 Port3 Port5 Port2 Port4 INVERT OR -K- pi -C- 180 1/3 Constant Breaker2Breaker1Breaker 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -400 -300 -200 -100 0 100 200 300 400 Time v o lt uncompensated voltage (v) Dr.P.Usha Rani/ Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation (2014) 108 REFERENCES 1. Chellai Benachaiba and Brahim Ferdi, “Voltage Quality Improvement Using DVR”, Electrical Power Quality and Utilization, Journal Vol. XIV, No. 1, pp. 39-45, 2008. 2. Chi-Seng Lam, Man-Chung Wong and Ying-Duo Han, “Voltage Swell and Over voltage Compensation with Unidirectional Power Flow Controlled Dynamic Voltage Restorer”, IEEE Transactions on Power Delivery, Vol. 23, No. 4, pp. 2513-2521, 2008. 3. Paisan Boonchiam, and Nadarajah Mithulanathan, “Detailed Analysis of Load Voltage Compensation for Dynamic Voltage Restorer”, Thammasat International Journal of Science and Technology, Vol. 11, No. 3, pp. 1-6, 2006. 4. Mahinda Vilathgamuwa D., Choi S. S. and Wijekoon H.M, “Interline Dynamic Voltage Restorer: A Novel and Economical Approach for Multiline Power Quality Compensation”, IEEE Transactions on Industry Applications, Vol. 40, No. 6, pp. 1678-1685, 2004. 5. Mahinda Vilathgamuwa D., C.J.Gaanayake, P.C.Loh, Y.W.Li, “Voltage sag compensation with Z source inverter based dynamic voltage restorer”, IEEE Industrial Electronics Conference, pp. 2242- 2248, 2006. 6. Mahinda Vilathgamuwa D., Choi S. S. and Wijekoon H.M, “A Novel Technique to Compensate Voltage Sags in Multiline Distribution System- The Interline Dynamic Voltage Restorer”, IEEE Transactions on Industrial Electronics, Vol.53, No.5, pp. 1603-1611, 2006. 7. Nguyen P. T. and Tapan K. Saha, “DVR against Balanced and Unbalanced Voltage Sags: Modelling and Simulation”, Proceedings of the IEEE Industrial Electronics Conference, pp. 1-6, 2004. 8. Usha Rani P. and Rama Reddy S, “Digital Simulation of an Interline Dynamic Voltage Restorer for Voltage Compensation”, International conference on Computer, Communication and Electrical Technology ICCCET, IEEE Xplore 978- 1-4244-9391-3/11, pp. 133-139, 2011. 9. Usha Rani P. and Rama Reddy S, “Modeling and Simulation ZSI based DVR for voltage compensation”, International conference on Computer, Communication and Electrical Technology ICCCET, IEEE Xplore 978-1-4244- 9391-3/11, pp. 90-96, 2011. 10. Usha Rani P. and Rama Reddy S, “Voltage sag / swell compensation in an interline dynamic voltage restorer”, International conference on Emerging Trends in Electrical and Computer Technology, ICETECT, IEEE Xplore 978-1-4244-7925-2/11, pp. 309-314, 2011. 11. Usha Rani P. and Rama Reddy S, “Voltage sag / swell compensation using Z-source inverter based dynamic voltage restorer”, International conference on Emerging Trends in Electrical and Computer Technology ICETECT, IEEE Xplore 978-1-4244- 7925-2/11, pp. 268-273, 2011. 12. Usha Rani P, “Voltage Swell Compensation in an Interline Dynamic Voltage Restorer’, Journal of Scientific and Industrial Research, Vol.73, No.1, pp.29-32, 2014. 13. Usha Rani P, “Modelind and simulation of MLI based Interline Dynamic Voltage Restorer’, Australian Journal of Basic and Applied Sciences, Vol.8, No.2, pp.162-167, 2014. P. Usha Rani is Professor in Electrical and Electronics Engineering Department, R.M.D. Engineering College, Chennai, India. She received her B.E. degree in Electrical & Electronics Engineering from the Government College of Technology, Coimbatore, India, M.E. degree in Power Systems from College of Engineering, Anna University, Chennai, India and PhD in the area of Power Electronics and Drives from Anna University, Chennai, India. She has published over 26 technical papers in international and national journals / conferences proceedings (IEEE Xplore-5). She has 17 years of teaching experience. Her earlier industrial experience was with Chemin Controls, Pondicherry, India. Her research interests on application of Power Electronics to Power Quality problems and FACTS. She is life member of Indian Society for Technical education and member if IEEE.