Transactions Template JOURNAL OF ENGINEERING RESEARCH AND TECHNOLOGY, VOLUME 2, ISSUE 4, DECEMBER 2015 217 Accurate Quadrature Encoder Decoding Using Programmable Logic Yassen Gorbounov Y.Gorbounov is with the Department of Automation of Mining Production, University of Mining and Geology “St. Ivan Rilski”, Sofia, Bulgaria, e-mail: y.gorbounov@mgu.bg Abstract— the quadrature encoder (or incremental detector) is amongst the most widely used positional feedback devices for both rotational and linear motion machines. It is well known that in conventional circuits for quadrature signals decoding, an error emerges during the direction change of the sensor movement. In some situations this error can be accumulative but in any case it provokes a position error, that is equal to the resolution (one pulse) of the sensor. A corrective algorithm is proposed here that fully eliminates this type of error. It is an improvement over a previous research of the author which is much simpler and resource saving without compromising the performance of the device. A Xilinx CPLD platform has been chosen for the experiments. The inherent parallelism of programmable logic devices permits a multi-channel CNC machine to be fully served by a single chip. This approach outperforms the capabilities of any conventional microcontroller available on the market. Index Terms— Quadrature encoder, incremental encoder, angular position measurement, motion control, programmable logic, parallel algorithms. I INTRODUCTION In motion control, the quadrature encoder can be of a ro- tary or linear-type, with an optical or magnetic sensing prin- ciple, which gives information about both the relative posi- tion and the motional direction of a shaft. This device is directly connected to the numerical sub-system which con- trols the motor. Since it lies in the feedback path, it plays a very important role in keeping the system up and running. A missing pulse can lead to a major miscalculation and can even damage the mechanical drive system. The basic princi- ple of operation is as follows: the two phases A and B of the encoder are displaced in 90 degrees each other, which allows the phase difference to be used as a sign that shows the movement direction. The time diagram of these two pulse sequences is given in fig.1. If the upper sequence determines conditionally the movement in positive direction, the pulse sequence from fig.2 visualizes the outputs A and B in the negative move- ment direction. A case of direction reverse is illustrated in fig.3 by the up- per two rows. In order to augment the resolution of the sensor, the frequency of pulses is being quadrupled by generating a pulse on every rising or falling edge and these higher frequen- cy pulses are divided into two separate channels indicating positive and negative direction of movement (the lower two rows). The transformation of the signals given in fig.3 gives op- portunity for easy position measurement, using simple Figure 1 A time diagram of a positive direction pulse sequence Figure 2 A time diagram of a negative direction pulse sequence Figure 3 A case of direction change Yassen Gorbounov / Accurate Quadrature Encoder Decoding Using Programmable Logic (2015) 218 up/down counter and easy speed measurement by using an ordinary low pass filter. II THE ESSENCE OF THE PROBLEM The conventional electrical circuit element commonly used to determine the direction of movement is the D-type flip- flop. The way it works is depicted in fig.4. When Dir=1 the direction of the movement is positive and when Dir=0 - it is negative. As can be seen in the figure there is some delay between the actual direction change and the time of sensor activation. It is obvious from the time diagram that the two-circled pulses are on the wrong chan- nel. If the two channels are wired to an up/down counter this will provoke an error of 2 count pulses. This is equal to the resolution of the incremental encoder, which in some cases might be of significant importance. The general block diagram that is commonly used for the detector implementation is given in fig.5. A corrective cir- cuit will be discussed further that updates the D-type flip- flop appropriately and fully compensates for the erroneous situations. There exist many solutions on the market that deal with the decoding of incremental encoders. Some of them are processor-based solutions [4], [8], [14], others are FPGA- based [9], [10], [12] and there exist also dedicated integrated circuits [6], [7], to mention just a few. Although the problem is analyzed deeply and broadly discussed in the litterature, none of these sources fully handles all the reversal situations and the arising errors and thus none of them fully compen- sates the error. Based on a previous research of the author, the aim of this work is to offer an optimized solution of the problem i.e. full elimination of the error, which is compact, resource saving and suitable for parallel implementation using programmable logic devices (PLD). III DEFINITION OF ERRONEOUS SITUATIONS There are 8 situations that can lead to an error during direc- tion reversal. Four of them happen on negative clock transi- tion (see signal B in fig.4) and they are shown in fig.6. Another four happen on positive clock transition which is shown in fig.7. Figure 4 A conventional direction identification circuit and the emerging error Figure 5 The conventional device block diagram Figure 6 The reverse situations, emerging errors dur- ing the negative edge Figure 7 The reverse situations, emerging errors during the positive edge Yassen Gorbounov / Accurate Quadrature Encoder Decoding Using Programmable Logic (2015) 219 Every one of them is assigned a letter from the Greek al- phabet, namely α, β, γ, δ, ε, δ, ε and ζ. All the situation can be described as follows: α – the original movement is forward, the system reverses after the second positive edge. The performed transition is forward-backward. β – the original movement is backward, the system reverses after the second positive edge. The performed transition is backward-forward. γ – the original movement is forward, the system reverses after the first positive edge. The performed transition is forward-backward. δ – the original movement is backward, the system reverses after the first positive edge. The performed transition is backward-forward. ε – the original movement is forward, the system reverses after the second negative edge. The performed transition is forward-backward. δ – the original movement is backward, the system reverses after the second negative edge. The performed transition is backward-forward. ε – the original movement is forward, the system reverses after the first negative edge. The performed transition is forward-backward. ζ – the original movement is backward, the system reverses after the first negative edge. The performed transition is backward-forward. In some situations the error emerging during direction re- versal is accumulative. This is the situation when one of the ε or ζ case combines with the other six. The probability this to happen is 0.43 and it is given in eq. 1 where P denotes the probability and C denotes the combination: IV OPERATION OF THE ERROR CORRECTION CIRCUIT The entire device structure is implemented in Verilog HDL using the behavioral modeling approach [2], [3], [5] and represents in fact a simple finite state machine. For the sake of readability here it is presented in schematic form which is much easier to adopt. The schematic is separated in three major parts. At first the input frequency obtained by the encoder channels A and B is being quadrupled in order to increase the sensor resolution (see fig.8). This is done using one D flip-flop per channel (a delay element) and a very simple XOR method. This way a short pulse (Ap and Bp) is pro- duced on every rising and falling edge. Both channels are combined with an AND logic gate. At the same time a con- ventional direction detector algorithm works in parallel. This signal contains the error and it will be processed further. The second stage schematic is shown in fig.9. It is com- prised of one shift-register per channel which is clocked by the quadrupled frequency of the inputs. The AND gate per- mits to filter out every two consecutive pulses that may appear on the channel. The presence of such a sequence indicates the need for direction correction. The output of this circuit serves as a "reset direction" signal which emerges precisely at the time of reversal. The "erroneous direction" and the "reset direction" sig- nals are both used in the schematic shown in fig.10 which represents the corrective circuit. Its purpose is to set or reset the direction signal at the exact times of reversal. Finally, the quadrupled frequency and the correct direc- tion signals are used to drive a multiplexer circuit that out- Figure 9 Direction reset circuit Figure 8 Frequency quadrupling and erroneous direction detector circuit Figure 10 Corrective and output forming circuit Yassen Gorbounov / Accurate Quadrature Encoder Decoding Using Programmable Logic (2015) 220 puts the Up and Down signals which may be used further by an up/down counter. The entire device is built and experimented using a Xil- inx CoolRunnerII CPLD programmable logic device [17]. Simulation results are shown in fig.11 to fig.18, each one corresponding to a situation represented in fig.6 and fig.7 respectively. What is not discussed here is the problem of synchoniza- tion of the inputs A and B which are asynchronous in regards to the internal clock domain of the device and thus may lead to metastability issues. These problems are very well re- vealed in [13], [15], [16]. A convenient digital filtering method for ignoring glitches is proposed in [9], [14]. The corrective algorithm implementation occupies 14 macrocells and 27 product terms compared with 17 macro- cells and 28 product terms occupied by the design proposed in [1]. That is an improvement of 17.65 % in macrocells and permits the design to fit in a single function block, in terms of Xilinx CPLD technology. The input clock frequency is required to be at least 4 times higher than that of the quadru- pled frequency while the upper limit is bounded by the re- sources of the chosen PLD. The abilities for parallel algo- rithm processing inherent to programmable logic devices gives opportunity for a multi-axis CNC machine to be fully served by a single chip. Figure 11 Case Alpha - forward-backward transition Figure 12 Case Beta - backward -forward transition Figure 13 Case Gamma - forward-backward transition Figure 14 Case Delta - backward-forward transition Figure 15 Case Epsilon - forward-backward transition Figure 16 Case Zeta - backward-forward transition Figure 17 Case Eta - forward-backward transition Figure 18 Case Theta - backward-forward transition Yassen Gorbounov / Accurate Quadrature Encoder Decoding Using Programmable Logic (2015) 221 V CONCLUSION When it is about a high precision servo drive or motion system with a quadrature encoder-based positional feedback a fast and expensive sensor and decoding logic may be re- quired. The proposed method suggests an error-free algo- rithm that handles all the erroenous situations emerging during direction reversal. The implementation of such a device is cheap and easy to be done using reconfigurable programmable logic device. Due to the capabilities for paral- lel algorithm execution multiple devices of the proposed type can be implemented on a single chip - be it of a CPLD or FPGA type. This approach outperforms the capabilities of any conventional microcontroller available on the market. REFERENCES [1] C. Pavlitov, Y. Gorbounov: Precise Incremental Decod- ing Device. In: EDPE 2005, Dubrovnik, Croatia, ISBN- 10 9536037432, 2005. [2] M. Mano: Digital Design, 3ed, Prentice Hall, ISBN-10: 8120320956, 2002. [3] S. Palnitkar: Verilog HDL, 2ed, Prentice Hall, ISBN-10: 0132599708, 2003. [4] H. Toliyat, S. Campbell, DSP-Based Electromechanical Motion Control, ISBN 0-8493-1918-8, CRC Press, 2004. [5] C. Pavlitov, Y. Gorbounov, Programmable Logic Devic- es in Electromechanics (BOOK in Bulgarian), Technical University of Sofia, ISBN 978-954-438-645-0, 2007. [6] LS7184N - Quadrature Clock Converter and Decoder, LSI Computer Systems Inc., 1235 Walt Whitman Road Melville, NY 11747-3010, USA, 2015. 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Clark, Intelligent Incremental Encoder System Devel- opment, May 2009, Available at: http://www.secondvalleysoftware.com/documentation/p dfs/encoder.pdf [15] D. Kinniment, K. Heron, G. Russell, Measuring Deep Metastability, Newcastle University, UK, Available at: http://www.async.org.uk/David.Kinniment/Research/pa pers/Async2006.pdf [16] A. Cantoni, J. Walker, T. Tomlin, Characterization of a Flip-Flop Metastability Measurement Method, IEEE Transactions on Circuits and Systems, Vol.54, No.5, DOI:10.1109/TCSI.2007.895514, May 2007 [17] CoolRunner-II CPLD Family, Application Note DS090 (v3.1), Xilinx Ltd., Sep. 2008.Available at: http://www.xilinx.com/support/documentation/data_she ets/ds090.pdf Yassen Gorbounov The author received a PhD degree from the Faculty of Automation at Technical University of Sofia, Depart- ment of Electrical Drives Automation in 2013. He is a chief assis- tant professor in the University of Mining and Geology "St. Ivan Rilski", Sofia and delivers lectures in ―Measurement of nonelectric quantities‖, ―Microprocessor systems‖ and ―Digital Systems‖. He is a member of the IEEE, Region 8, the Federation of the Scientific and Engineering Unions in Bulgaria (FNTS) and John Atanasoff Union of Automation and Informatics (UAI). He is an author or co- author of over 20 journal and conference papers and is a co-author of 1 book. His research interests include automatic control of elec- trical drives, switched reluctance motor and generator control, application of neural networks and fuzzy logic for motor control, parallel processing algorithms with programmable logic devices, digital control of electromechanical systems.