Microsoft Word - tpel.doc Mathematical Problems of Computer Science 35, 137--139, 2011. 137 Compact High Performance Algorithm for Convolutional Decoder Arsen Hakhoumian, Tigran Zakaryan, Aramazd Muzhikyan and Vahan Nikoghosyan Institute of Radiophysics and Electronics, Armenian National Ac.Sci. Alikhanian 1, Ashtarak, 0203, Armenia Abstract An efficient algorithm for convolutional decoder running in the mode of soft decision (1/2, K=7, 3-bit decision) in a FPGA Virtex-II is proposed. The results show that although increasing the length of the cutoff buffer improves the signal to noise ratio by 2dB, but it can significantly increase calculation time, which exponentially depends on the length of the cutoff buffer. At the optimal length of the cutoff buffer equal to 7, the obtained throughput is estimated up to 14Mbps. References [1] M Hosemann. R.Habendorf and G.Fettweis, “Hardware-software codesign of A 14.4mbit - 64 State viterbi decoder for an application-apecific digital signal processor”, IEEE Workshop on Signal Processing Systems, pp. 45-50, 2003. [2] M.Röder and R.Hamzaoui, “Fast tree-trellis list viterbi decoding”, IEEE Transactions on Communications, vol. 54, no. 3, pp. 453-461, 2006 [3] J.Campos and R.Cumplido, “A runtime reconfigurable architecture for viterbi decoding”, 3rd International Conference on Electrical and Electronics Engineering , pp. 1-4, 2006. ´³ñÓñ ϳï³ñáճϳÝáõÃÛ³Ùµ ÷³ÃáõÛóÛÇÝ ³å³Ïá¹³íáñÙ³Ý ë»ÕÙ ³É·áñÇÃÙ ². гËáõÙÛ³Ý, î. ¼³ù³ñÛ³Ý, ². ØáõÅÇÏÛ³Ý ¨ ì. ÜÇÏáÕáëÛ³Ý ²Ù÷á÷áõÙ ²é³ç³ñÏíáõÙ ¿ ³ñ¹Ûáõݳí»ï ³å³Ïá¹³íáñÇãÇ ÷³ÃáõÛóÛÇÝ ³É·áñÇÃÙ, áñÝ ³ß˳ïáõÙ ¿ áñáßáõ٠ϳ۳óÝ»Éáõ ÷³÷áõÏ é»ÅÇÙáõÙ (1/2, K=7, áñáßáõ٠ϳ۳óÝ»Éáõ 3 µÇÃ) FPGA Virtex-II ѳٳϳñ·áõÙ: êï³óí³Í ³ñ¹ÛáõÝùÝ»ñÁ óáõÛó »Ý ï³ÉÇë, áñ ÏïñÙ³Ý µáõý»ñÇ »ñϳñáõÃÛ³Ý ÏñÏݳÏÇ Ù»Í³óáõÙÁ ãÝ³Û³Í ¨ ѳݷ»óÝáõÙ ¿ ³½¹³Ýß³Ý/³ÕÙáõÏ Ñ³ñ³µ»ñáõÃÛ³Ý 2 ¹´-áí ɳí³óÙ³ÝÁ, ϳñáÕ ¿ ¿³Ï³Ýáñ»Ý ٻͳóÝ»É Ñ³ßí³ñÏÇ Å³Ù³Ý³ÏÁ, áñÁ óáõóã³ÛÇÝ Ï³Ëí³ÍáõÃÛáõÝ áõÝÇ ÏïñÙ³Ý µáõý»ñÇ »ñϳñáõÃÛáõÝÇó: K=7 ûåïÇÙ³É »ñϳñáõÃÛ³Ý Ñ³Ù³ñ ëï³óíáõÙ ¿ 14 ص/í ³é³í»É³·áõÛÝ áõݳÏáõÃÛáõÝÁ: