Mathematical Problems of Computer Science 54, 88–95, 2020.

UDC 004.33

BIST Architecture for Magnetic Memories

Armen V. Babayan

National Polytechnic University of Armenia

e-mail: Armen.Babayan@synopsys.com

Abstract

Magnetic random-access memory (MRAM) is one of the emerging memory tech-
nologies, which can be considered as the next universal memory because of its good
parameters. Nevertheless, this type of memory is not guaranteed from defects and it
is very important to understand the fault typology and develop a test solution that
addresses these faults. In this paper a Built-in Self-Test (BIST) solution is presented,
which is specifically tailored for MRAMs and efficiently deals with MRAM specific
faults.

Keywords: Memory BIST, Memory testing, Magnetic memory, Emerging mem-
ory, System on Chip.

1. Introduction

Innovative technologies require effective solutions to increase the reliability of systems in
the industry of the integrated circuits (IC). Devices like memories are sensitive to external
influences that can cause a system failure. Nowadays memories are the most commonly used
devices in electronics. In recent decades, different types of memories have been invented,
each of which had certain parametric and functional characteristics. Few examples of such
memories can be found in the literature, as demonstrated below.

• Macro block, which consists of 0.021um2 SRAM bit cells. Macro operates up to 2GHz
at 0.95V. 5nm FinFET technology is used [1].

• 16Gb DRAM with speed 18Gb/s/pin and 1.35V VDD [2].

• 16Tb Flash memory is proposed in [3], which works with speed 1.8GB/s/pin. 20nm
CMOS technology is used.

On the other hand, frequencies are getting higher, the volume of the information extends
in most of devices (for example, more storage is required for better quality of the photos
in smartphones), and the existing memories (SRAM, DRAM, existing NVM) become insuf-
ficient for new challenges. MRAM is one of the emerging memories, which has promising
parameters, that is why it is also important to take care of the reliability of this type of

88



A. Babayan 89

memory. Built-in Self-Test (BIST) is an effective solution that is usually used to test em-
bedded memories and can be adopted for MRAM as well. MRAM has the perspective to
be a universal memory , as it is non-volatile and has a speed close to SRAM and a density
close to DRAM at the same time.

2. Preliminaries

2.1. MRAM Structure

MRAM cell consists of a transistor and a device called a magnetic tunnel junction (MTJ).
It consists of two ferromagnetic layers separated by an insulator (Figures 1,2,3). MTJ is a
based on tunnel magnetoresistance (TMR) which occurs in MTJ and is quantum mechanical
phenomenon. Electrons can tunnel from one layer to another because the insulator layer
is very thin. One of the layers has a fixed direction of spins. The direction of spins of
the second layer can be changed by applying voltage between two layers. MTJ can be
represented as a variable resistance, which can be changed depending on the direction of
spins in ferromagnetic layers. There are parallel and antiparallel cases. When magnetic
spins are parallel, the resistance of the MTJ becomes lower, which corresponds to level ”0”.
Accordingly, for a logical level ”1”, the MTJ is in an antiparallel state with high resistance.

Fig. 1. MRAM bit cell.

Fig. 2. MRAM bit cell schematic.



90 BIST Architecture for Magnetic Memories

Fig. 3. MTJ schematic.

2.2. Faults specific to MRAM

Since MRAM has a different manufacturing technology in contrast to CMOS, it is required to
explore defects, which can occur during manufacturing (resistive faults are shown in Figure
4). There are also other faults, which are not described because of MTJ nature. The main
reason is the clear tunneling phenomenon, which has a certain probability. For example, the
insulation layer thickness can change the MTJ resistance which can cause read failure. Some
of MRAM specific faults are described in Table 1.

Table 1: Faults specific to MRAM

Stuck at P MTJ is stuck at the parallel state (low resistance for
MTJ).

Stuck at AP MTJ is stuck at the antiparallel state (high resistance
for MTJ).

Open Weak connections between metals or other layers can
cause open defects and correspondingly open fault
because of high resistance.

Short Short between ferromagnetic layers can occur during
some manufacturing stages.

Transition fault It is not possible to write 0 when a bit cell caries
1, and vice versa (it is assumed that initially
memory has x value).

Coupling fault Switching of the current bit cell causes flipping of the
neighbor bit cell.

Incorrect read fault Incorrect value after read operation (it means that the
bit cell carries 0/1 but the read data is 1/0).



A. Babayan 91

Fig. 4. Resistive faults for one bit cell (in red area).

2.3. Algorithms for Testing MRAM

Several algorithms for MRAM testing are suggested in [4]-[6]. [4] also offers an automated
flow for defect injection and fault modeling, which is very useful for writing new test vectors
for certain faults. [5] suggests a test algorithm, which covers most of the resistive defects
described in the same paper. The proposed BIST architecture provides all the necessary
operations to detect the above-mentioned defects.

3. MRAM BIST

There are different architectures of testing systems for different types of memories. During
design implementation, it is important to take into account the hierarchical structure of the
design, which contains memories, their sharing mechanism, test efficiency for that system,
etc. Sometimes these and other factors make testing systems insufficient for executing certain
types of algorithm or do not meet the given specification. The suggested testing system
takes into account the above mentioned and other design specific difficulties. MRAM testing
system consists of two main components: MRAM Processor and MRAM Memory Controller
(Figure 5).

3.1. MRAM Memory Controller Components

Memory controller provides transmission of test data and control signals from processor
directly to the memory, as well as the memory output-related analyses in backward direction.
Controller has the following blocks as described in Table 2.

3.2. MRAM Processor Components

MRAM Processor Unit regulates connections and signals between memory controllers. It is
responsible for address, data (pattern), redundancy generation, and executing instructions.



92 BIST Architecture for Magnetic Memories

Fig. 5. Built-in Self-Test System.

Table 2: Memory controller’s main components

Comparator Compares output data with the expected ones. Sends
theresult of comparison to the processor.

Redundancy Allocator Makes repair signature according to error data.

It has a programmable buffer, which carries a march algorithm. Short introduction of some
processor blocks are described below in Table 3.

Table 3: BIST Processors main components

Address Generator Responsible for test address signal for the
memories in wrappers. Different addressing
modes are available.

Data Generator Responsible for test input data for the memories in
wrappers. Solid, checkerboard and other patterns
are available.

Redundancy Generator Collects repair data information from wrappers
to perform memory repair.

BIST Controller Controls march algorithm execution on memories
(Figure 6).

Trim Controller Executes search algorithms to find reference values
for MRAM memories for efficient testing.



A. Babayan 93

Fig. 6. Block Diagram for BIST flow.

4. Conclusion

Magnetic memory becomes more widespread nowadays thanks to its good characteristics
and is considered to be the next universal memory. Therefore, it is highly important to
well understand the faults inherent to this technology and develop a test solution addressing
these types of faults. In this work, fault universe for MRAM memories is investigated and a
specifically adjusted BIST architecture is proposed, which allows us to detect all these types
of faults. Among other features, the proposed BIST solution has an algorithm programmable
capability, which is used to code test algorithms for detecting specific fault types and an
efficient test trimming mechanism used for searching MRAM reference bits.

References

[1] T. J. Chang et al. “A 5-nm 135-Mb SRAM in EUV and high-mobility channel FinFET
technology with metal coupling and charge-sharing write-assist circuitry schemes for
high-density and low-VMIN applications”, in IEEE Int. Solid-State Circuits Conf.
(ISSCC), Dig. Tech. Papers, pp. 238-239, Dec. 2020.

[2] J. Baek et al. “A sub-0.85V, 6.4Gbp/s/pin TX-interleaved transceiver with fast wake-
up time using 2-step charging control and VOH calibration in 20nm DRAM process”,
in Symposium on VLSI Circuits Digest of Technical Papers, pp. 430-431, June 2018.

[3] J. Lee, “A 1.8 Gb/s/pin 16Tb NAND flash memory multi-chip package with F-chip
of toggle 4.0 specification for high performance and high capacity storage systems”, in
IEEE Symposium on VLSI Circuits, pp. 190-191, June 2020.

[4] S.M. Nair et al. “Defect injection, fault modeling and test algorithm generation
methodology for STT-MRAM”, IEEE International Test Conference (ITC), pp. 1-10,
2018.



9 4 BIST Architecture for Magnetic Memories

[5 ] I. Y o o n , A . Ch in t a lu r i a n d A . R a yc h o wd h u r y, \ E MA CS : E ± c ie n t MB IS T a r c h it e c -
t u r e fo r t e s t a n d c h a r a c t e r iz a t io n o f S TT-MR A M a r r a ys " , IE E E International Test
Conference (ITC), p p . 1 -1 0 , 2 0 1 6

[6 ] C. S u e t a l, \ W r it e d is t u r b a n c e m o d e lin g a n d t e s t in g fo r MR A M" , IE E E Transactions
on Very L arge Scale Integration (VL SI) Systems, vo l. 1 6 , n o . 3 , p p . 2 7 7 -2 8 8 , 2 0 0 8 .

Ü»ñ¹ñí³Í ûëï³íáñÙ³Ý ×³ñï³ñ³å»ïáõÃÛáõÝ

Ù³·ÝÇë³Ï³Ý ÑÇßáÕáõÃÛáõÝÝ»ñÇ Ñ³Ù³ñ

²ñÙ»Ý ì. ´³µ³Û³Ý

г۳ëï³ÝÇ ³½·³ÛÇÝ åáÉÇï»ËÝÇÏ³Ï³Ý Ñ³Ù³Éë³ñ³Ý

e-mail: Armen.Babayan@synopsys.com

²Ù÷á÷áõÙ

س·ÝÇë³Ï³Ý Ï³Ù³Û³Ï³Ý ÁÝïñáõÃÛ³Ùµ ÑÇßáÕáõÃÛáõÝÁ (MRAM) Ýáñ ųٳݳϳÏÇó
ï»ËÝáÉá·Ç³Ý»ñÇó Ù»ÏÝ ¿, áñÝ Çñ ɳí å³ñ³Ù»ïñ»ñÇ ßÝáñÑÇí ϳñáÕ ¿ ¹Çï³ñÏí»É
áñå»ë ѳçáñ¹ ѳٳåÇï³ÝÇ ÑÇßáÕáõÃÛáõÝ: ²ÛÝáõ³Ù»Ý³ÛÝÇí, ³Ûë ïÇåÇ ÑÇßáÕáõÃÛáõÝÁ
å³ßïå³Ýí³Í ã¿ ³Ýë³ñùáõÃÛáõÝÝ»ñÇó, ¨ ß³ï ϳñ¨áñ ¿ ѳëÏ³Ý³É ³Û¹ ³Ý-
ë³ñùáõÃÛáõÝÝ»ñÇ ¹³ë³Ï³ñ·áõÙÁ ¨ Ùß³Ï»É Ã»ëï³íáñÙ³Ý Ñ³Ù³Ï³ñ·, áñÁ ¹áõñë
ϵ»ñÇ ¹ñ³Ýó ѻ勉Ýùáí ³é³ç³óáÕ ë˳ÉÝ»ñÁ: ²Ûë Ñá¹í³ÍáõÙ Ý»ñϳ۳óí³Í ¿
Ý»ñ¹ñí³Í ûëï³íáñÙ³Ý Ñ³Ù³Ï³ñ· (BIST) Ù³·ÝÇë³Ï³Ý ÑÇßáÕáõÃÛáõÝÝ»ñÇ Ñ³Ù³ñ,
áñÁ ³ñ¹Ûáõݳí»ï Ï»ñåáí ѳÛïݳµ»ñáõÙ ¿ ³Û¹ ïÇåÇ ÑÇßáÕáõÃÛáõÝÝ»ñÇÝ Ñ³ïáõÏ
³Ýë³ñùáõÃÛáõÝÝ»ñÁ:

Submitted 14 07.20, accepted 17.11.20.

´³Ý³ÉÇ µ³é»ñ՝ ÑÇßáÕáõÃÛáõÝÝ»ñÇ Ý»ñ¹ñí³Í ûëï³íáñáõÙ, ÑÇßáÕáõÃÛáõÝÝ»ñÇ
ûëï³íáñáõÙ, Ù³·ÝÇë³Ï³Ý ÑÇßáÕáõÃÛáõÝ, Ýáñ³·áõÛÝ ÑÇßáÕ ë³ñù, ѳٳϳñ· µÛáõñ»ÕÇ
íñ³:



A. Babayan 9 5

Àðõèòåêòóðà âñòðîåííîãî ñàìîòåñòèðîâàíèÿ äëÿ

ìàãíèòíûõ ïàìÿòåé

Àðìåí Â. Áàáàÿí

Íàöèîíàëüíóé ïîëèòåõíè÷åñêèé óíèâåðñèòåò Àðìåíèè
e-mail: Armen.Babayan@synopsys.com

Àííîòàöèÿ

Ìàãíèòíàÿ ïàìÿòü ñ ïðîèçâîëüíûì äîñòóïîì (MRAM) - îäíà èç íîâûõ
ñîâðåìåííûõ òåõíîëîãèé, êîòîðàÿ áëàãîäàðÿ ñâîèì õîðîøèì ïàðàìåòðàì
ìîæåò ñ÷èòàòüñÿ ñëåäóþùåé óíèâåðñàëüíîé ïàìÿòüþ.Òåì íå ìåíåå, ýòîò òèï
ïàìÿòè íå ãàðàíòèðîâàí îò äåôåêòîâ, è î÷åíü âàæíî ïîíèìàòü òèïîëîãèþ
íåèñïðàâíîñòåé è ðàçðàáîòàòü òåñòîâîå ðåøåíèå, êîòîðîå óñòðàíÿåò îøèáêè
âûçâàííûå íåèñïðàâíîñòÿìè. Â ýòîé ñòàòüå ïðåäñòàâëåíî ðåøåíèå âñòðîåííîãî
ñàìîòåñòèðîâàíèÿ (BIST), êîòîðîå, â ÷àñòíîñòè, àäàïòèðîâàíî äëÿ MRAM è
ýôôåêòèâíî óñòðàíÿåò åãî ñïåöèôè÷åñêèå íåèñïðàâíîñòè.

Êëþ÷åâûå ñëîâà: ñàìîòåñòèðîâàíèå âñòðîåííîé ïàìÿòè, òåñòèðîâàíèå
ïàìÿòè, ìàãíèòíàÿ ïàìÿòü, íîâåéøàÿ ïàìÿòü, ñèñòåìà íà êðèñòàëëå.


	08_Armen_V__Babayan_MPCS_88_95 (1)
	Armen_18