Ratio Mathematica Volume 44, 2022 VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications Poongodi.S1 Asoda Sunayana Rani2 Abstract Data transmission in advanced space communications are suffering with the different types of noises. Further, these noises causeburst errors indata. Thus, the error correction codes (ECC) plays the major role to detect and correct the errors. However, the conventional hamming encoders, decoderswere detected and corrected only one bit error. Therefore, this work implementation the Multi-Bit Error Detection and CorrectionCodes (MBE-DCC) for multiple bits error detection and correction. Initially, MBE-DCC encoding operation is implemented by using generator matrix, which contains both identity bits and parity bits. Then, encoded code word is transmitted into the channel of space communication, where encoded data corrupted by different types of noises, errors. Therefore, the MBE-DCC decoding operation performed at receiver side of space communications, which corrected all the errors using syndrome detection, error location detection, and error correction modules. The simulations revealed that the proposed MBE-DCC resulted in superior performance than conventional ECC methods. Keywords: Multi-Bit Error Detection and Correction Codes, encoding, decoding, syndrome decoding, error analysis, error correction modules. AMS Classification:05C123 1Professor, Dept. of ECE, CMR Engineering College, Hyderabad. dr.poongodi@cmrec.ac.in 2PG student, CMR Engineering College, Hyderabad. sunayana7007@gmail.com 3Received on June 9th, 2022. Accepted on Sep 1st, 2022. Published on Nov30th, 2022. doi: 10.23755/rm.v44i0.897. ISSN: 1592-7415. eISSN: 2282-8214. ©The Authors. This paper is published under the CC-BY licence agreement. 107 mailto:dr.poongodi@cmrec.ac.in mailto:sunayana7007@gmail.com Poongodi.S & Asoda Sunayana Rani 1. Introduction The space communicationscontain the channel and to store a value memory is used in channel. In which Random Access Memory (RAM) [1] has been the developing and most compatible device in particular for microprocessor and microcontroller. Main memory helps to keep the processor or controller busy and to perform any task in a minimum time [2]. To achieve this on-chipmemory termed as cache memory is used. This type of main memory is developed and placed at different levels close to the processor on same die, additionally to reduce the access time of the processor for the data that to be processed from the main memory (RAM) [3]. Moreover, the data saved in the cache memory need to be the actual that has been stored during the write operation. Nevertheless, stored value need not be the same as that was stored. Probability of change in stored value is increasing linearly because of rapid change in semiconductor processing technology. To overcome this issue of reliability in cache memory ECC is imperative [4]. Various works [5,6] proposed three models on memory with ECC, of which first model is data communication between memory and cache, second model is the same that includes the additional copy. Last model is the cross-switch communication between the original and additional memory with ECC. For all the model’s memory designed is a simple single row address memory with ECC as a separate block [7]. ECC block for the memory is an additional hardware design which increases the delay in area, howeveradditional overhead in area and latency enhances the performance degradation of the system. Performance degradation of a system that includes cache memory can be improved, provided the decoding time for detection [8], correction and the ability to correct or detect with some failure should be a fraction of total memory design size. In recent studies memory with ECC is inherent for protecting the memory from errors in particular soft errors. Multiple Cell Upset (MCU) [9] denotes arbitrary number of cells which is repeatedly affected by soft error is random and most of the cases it is not adjacent. However due to scaling down of the gate width of transistors, density of transistors increases in this case occurrence of soft error has the tendency of dissemination. To mitigate this new and optimized coding algorithms are proposed and being proposed on adjacent error also called as burst errors. Most common adjacent errors are two, three termed as Double Adjacent [10], Triple Adjacent [11] respectively. However, the performance degradation of a system cannot be compromised for which optimized syndrome computation is considered. Therefore, the major contributions of this work are as follows: • Implementation of MBE-DCC for multiple bits error-detection and correction in space communication applications. • MBE-DCC encoder is developed with generator matrix, which generates the encoded code word. • Implementationof MBE-DCC decoder with syndrome detection, error location detection, and error correction modules. 108 VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications • Implementation of syndrome detection is introduced for detecting status of error, which results error presented or absented in encoded data. • Implementation of error location detection module for identifying the number of error bits with their position. • Implementation of error correction module for correcting all the errors in encoded data. Rest of the article is organized as follows: section 2 deals with literature survey, section 3 deals with the proposed MBE-DCC implementation, section 4 deals with analysis of results with performance comparison, section 5 concludes the article with possible future directions. 2. Literature survey Cosmic rays and IC packaging dye made from radioactive elements are few significant sources of soft error in cache memory. Furthermore, recent studies on cache memories have shown that reliability issues in cache memory for application that are used to store or during processing of data is significant concern. Especially graphical processing units [12] currently developed by NIVIDIA, AMD and INTEL are designed with high bandwidth cache memories and frequently subjected to reliability problems. To substantive this, in [13] authors presented a flexible ECC designed for 32-byte cache memory which also consumes low energy for data fetching. In [14] authors compared different error detection techniques and developed a method which has error guard coverage of 97.9 % using tag in cache. The tags are used for index identification. A limitation is that the adjacent location tag in cache memory may be having the same bits that leads to a faulty read or write operation in the cache memory. The change in bits of tag is due to alpha particles. This can be reduced by deploying ECC, SEC – DED, In-Cache Replication (ICR), and in combination of SEC– DED [15], ICR and SEC – DED parity. However, the proposed ICR method has good fault coverage. In [16] authors proposed counter, shifter, multiplexer and comparator were used and the additional peripherals added to the development of ICR contributed to additional overhead in area. Even after adding the addition peripherals, the delay and area are found to be less. This technique [17] lags because the disadvantage is if the size of the cache increases in terms of level 1, 2, the method proposed increases the complexity of peripherals in 11 proportion to the chance in the size of cache. Also, here only one error is possible to correct. Moreover, triple adjacent location is not addressed. In [18] authors proposed a method to reduce energy overhead in DRAM (cache) achieved through ECC. DRAM is not modified in design instead, for the usual DRAM a new ECC that access or decodes only the error word is presented. Conventionally only encoded input data is stored, which is decoded to correct or detect the soft error using ECC in a memory. In contrary only error word is corrected using hamming code and error in a word is detected by parity codes. In [19] authors also proposed a DRAM (cache) with ECC, unlike other methods [20] in particular proposed a method that detects hard errors using a 109 Poongodi.S & Asoda Sunayana Rani BIST and build in self repair circuits on a chip. ECC that is capable to detect and correct physical fault and soft error is achieved through redundancy circuit or spare circuit and ECC respectively. However, study outlined above of DRAM with ECC [21] is limited to detect and correct two bits and single bit respectively and correcting soft error beyond one error is not possible. Most widely implemented memory circuit is made to store data in SRAM. There are few applications in which SRAM are neither used as cache nor main memory. For instance, SRAM is used as a configurable switch, programmed to connect the logic blocks, technically termed as routing this architecture [22] is implemented in commercial FPGA ‘s such as Xilinx virtex 4 and Altera stratix, moreover SRAM ‘s is used as configuration frames, which occupies more than 80% area in FPGA, such as Xilinx virtex 6 and FPGA of Altera family. However, both reconfigurable and configurable frames designed using SRAM are most probably sensitive to soft errors. In [23] authors proposed a scheme to correct multiple bits upset in configurable frame of FPGA. To detect MBU by combining scrubbing and erasure code additionally to detect error Interleaving-n-Dimensional (InD) method is also proposed. This is also implemented in Virtex-6 XLV240T, which has less overhead in area. Since in proposed InD method [24], with reduced repeated parity bits in all dimensions at regular intervals helps for less area occupation in the SRAM. In [25] authors proposed also presented error correction for switch boxes that are built using SRAM, also mitigation in soft error is achieved through redundancy method. In which zero optimized SRAM are used for interconnection and one optimized SRAM are redundant interconnection termed short and open faults respectively. However major work presented is on optimized routing algorithm. 3. Proposed Method This section gives the detailed analysis of proposed MBEC method. Figure 1 shows the flowchart of proposed MBEC method.Theproposed MBE-DCC is implemented for multiple bits error-detection and correction in space communication applications.Initially, MBE-DCC encoder is developed with generator matrix, which generates the encoded code word. Here, the matrix multiplication is operation is performed that the generator matrix and data input, which generates the code word. Then, the code-word is transmitted in channel of space engineering, where data bits are corrupted by different types of errors and noises. Further, MBE-DCC decoder is developed with syndrome detection, error location detection, and error correction modules.Here, syndrome detection is implemented for detecting status of error, which results error presented or absented in encoded data.Then, error location detection module is introduced for identifying the number of error bits with their position. Then, error correction module is developed for correcting all the errors in encoded data. 110 VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications Figure 1.Proposed MBE-DCC flowchart 3.1. MBE-DCC Encoding The operation of MBE – DCCencoding is achieved by performing the mathematicalmatrix multiplication between generator matrix and data input. 𝑉 = 𝐷𝐺 (1) Here, 𝑉 is the encoded code word, G is the generator matrix, 𝐷 is the input data. All of them are binary linear block codes. The process used to design these codes is based on some rules for linear block codes construction. In this paper, the proposed codes are also binary linear block codes and obey similar construction rules. Normally, the binary codes are described by the number of data-bits, k, redundancy bits, (n − k), and the block size of the encoded-word, n. An (n, k) code is defined by its generator matrix G or parity check matrix H in (2) where 𝐼𝑘×𝑘 is the identity matrix, P is the matrix with size k × (n − k), and 𝑃 𝑇 is the transpose of P. In the encoding process, the generator matrix G is used to encode the data bits through the process. Table 1. Construction of generator matrix. C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C 17 C 18 C 19 C 20 C 21 C 22 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 111 Poongodi.S & Asoda Sunayana Rani 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 1 shows the final constructed generator Matrix, which contains identity matrix and parity bits. Here, parity bits contain size as 16x7, which are ranged from all rows with C0- C6 columns. Further, the size of identity bits contains size as 16x16 i.e., all rows with C7- C22columns. The size of data is 16 bits as follows 𝐷 = [𝐷1, 𝐷2, 𝐷3, 𝐷4, 𝐷5, 𝐷6, 𝐷7, 𝐷8, 𝐷9, 𝐷10, 𝐷11, 𝐷12, 𝐷13, 𝐷14, 𝐷15, 𝐷16] (3) Finally, encoding operation is achievedthrough calculation of check bits (C1 to C7)as follows: 𝐶1 = 𝐷1⨁𝐷4⨁𝐷6⨁𝐷8⨁𝐷9⨁𝐷10⨁𝐷14 (4) 𝐶2 = 𝐷2⨁𝐷4⨁𝐷5⨁𝐷7⨁𝐷8⨁𝐷11⨁𝐷15 (5) 𝐶3 = 𝐷3⨁𝐷7⨁𝐷11⨁𝐷13⨁𝐷16⨁𝐷10 (6) 𝐶4 = 𝐷1⨁𝐷4⨁𝐷8⨁𝐷10⨁𝐷12⨁𝐷13 (7) 𝐶5 = 𝐷2⨁𝐷5⨁𝐷6⨁𝐷7⨁𝐷8⨁𝐷13⨁𝐷14 (9) 𝐶6 = 𝐷2⨁𝐷6⨁𝐷7⨁𝐷11⨁𝐷13⨁𝐷16 (10) 𝐶7 = 𝐷3⨁𝐷6⨁𝐷9⨁𝐷11⨁𝐷12⨁𝐷13⨁𝐷15⨁𝐷16 (11) Finally, encoding operation is achieved as follows: 𝑉 = [ 𝐶1, 𝐶2, 𝐶3, 𝐶4, 𝐶5, 𝐶6, 𝐶7, 𝐷1, 𝐷2, 𝐷3, 𝐷4, 𝐷5, 𝐷6, 𝐷7, 𝐷8, 𝐷9, 𝐷10, 𝐷11, 𝐷12, 𝐷13, 𝐷14, 𝐷15, 𝐷16 ] (12) 3.2 MBE-DCC Decoding The MBE-DCC decoding is consisting of syndrome detection, error location detection and error correction stages. The encoded output 𝑉 is transmitted into space communication channel, where different types of noises were added. 𝑅 = 𝑉 + 𝐸 𝑅𝐶 = [𝐶1, 𝐶2, 𝐶3, 𝐶4, 𝐶5, 𝐶6, 𝐶7] + [𝐸1, 𝐸2, 𝐸3, 𝐸4, 𝐸5, 𝐸6, 𝐸7] 𝑅𝐷 = [𝐷1, 𝐷2, 𝐷3, 𝐷4, 𝐷5, 𝐷6, 𝐷7, 𝐷8, 𝐷9, 𝐷10, 𝐷11, 𝐷12, 𝐷13, 𝐷14, 𝐷15, 𝐷16] + [𝐸8, 𝐸9, 𝐸10, 𝐸11, 𝐸12, 𝐸13, 𝐸14, 𝐸15, 𝐸16, 𝐸17, 𝐸18, 𝐸19, 𝐸20, 𝐷𝐸21, 𝐸22, 𝐸23] 𝑅 = [𝑅𝐶, 𝑅𝐷] 𝑅 = [ 𝑅𝐶1, 𝑅𝐶2, 𝑅𝐶3, 𝑅𝐶4, 𝑅𝐶5, 𝑅𝐶6, 𝑅𝐶7, 𝑅𝐷1, 𝑅𝐷2, 𝑅𝐷3, 𝑅𝐷4, 𝑅𝐷5, 𝑅𝐷6, 𝑅𝐷7, 𝑅𝐷8, 𝑅𝐷9, 𝑅𝐷10, 𝑅𝐷11, 𝑅𝐷12, 𝑅𝐷13, 𝑅𝐷14, 𝑅𝐷15, 𝑅𝐷16 ] Here, 𝑉 is the encoded code word, which stores into memory or transmitted into channel. Further, 𝐸 represents the error and 𝑅 represents the received vector with error. 112 VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications 𝑆 = 𝑅. 𝐻𝑇 (6) Here, 𝑆 represents the syndrome value, 𝐻 represents the parity check matrix and it is constructed from generator matrix as shown in Table 2. The size of identity bits (𝐼) are 7x7 i.e., all rows with H1-H7columns and size of the parity bits (𝑃) are 7x16 i.e., all rows with H8-H23columns. Further, if the 𝑆 is zero, which indicates no errors in received data. Further, if the 𝑆 is not equal to zero, which indicates errors presented in received data. Table 2. Construction of parity check matrix. H 1 H 2 H 3 H 4 H 5 H 6 H 7 H 8 H 9 H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 2 0 H 2 1 H 2 2 H 2 3 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 R C 1 R C 2 R C 3 R C 4 R C 5 R C 6 R C 7 R D 1 R D 2 R D 3 R D 4 R D 5 R D 6 R D 7 R D 8 R D 9 R D 1 0 R D 1 1 R D 1 2 R D 1 3 R D 1 4 R D 1 5 R D 1 6 Finally, the syndrome calculation is simplified as follows: 𝑆1 = 𝑅𝐶1⨁𝑅𝐷1⨁𝑅𝐷4⨁𝑅𝐷6⨁𝑅𝐷8⨁𝑅𝐷9⨁𝑅𝐷10⨁𝑅𝐷14 𝑆2 = 𝑅𝐶2⨁𝑅𝐷2⨁𝑅𝐷4⨁𝑅𝐷5⨁𝑅𝐷7⨁𝑅𝐷8⨁𝑅𝐷11⨁𝑅𝐷15 𝑆3 = 𝑅𝐶3⨁𝑅𝐷3⨁𝑅𝐷7⨁𝑅𝐷11⨁𝑅𝐷13⨁𝑅𝐷16⨁𝑅𝐷10 𝑆4 = 𝑅𝐶4⨁𝑅𝐷1⨁𝑅𝐷4⨁𝑅𝐷8⨁𝑅𝐷10⨁𝑅𝐷12⨁𝑅𝐷13 𝑆5 = 𝑅𝐶5⨁𝑅𝐷2⨁𝑅𝐷5⨁𝑅𝐷6⨁𝑅𝐷7⨁𝑅𝐷8⨁𝑅𝐷13⨁𝑅𝐷14 𝑆6 = 𝑅𝐶6⨁𝑅𝐷2⨁𝑅𝐷6⨁𝑅𝐷7⨁𝑅𝐷11⨁𝑅𝐷13⨁𝑅𝐷16 𝑆7 = 𝑅𝐶7⨁𝑅𝐷3⨁𝑅𝐷6⨁𝑅𝐷9⨁𝑅𝐷11⨁𝑅𝐷12⨁𝑅𝐷13⨁𝑅𝐷15⨁𝑅𝐷16 Then, based on syndrome values error locations were identified using bit pattern matching process. It is explained by following example. 𝐷 = [1,1,0,1,1,1,0,0,1,1,0,0,1,1,1,1] Then, 𝐶values are calculated using Equations (4)-(11) and resulted as follows: 𝐶 = [0,0,1,0,1,0,1] Then, encoded codeword V becomes, 𝑉 = [0,0,1,0,1,0,1,1,1,0,1,1,1,0,0,1,1,0,0,1,1,1,1] 113 Poongodi.S & Asoda Sunayana Rani Consider 4 bits are corrupted and error occurred in [D2, D3, D4, D5] positions of 𝑉. Then, R becomes 𝑅 = [0,0,1,0,1,0,1,1,0,1,0,0,1,0,0,1,1,0,0,1,1,1,1] The error locations are identified performing all combinations of XOR in H-matrix columns and the XOR outcome will be matched with syndrome for anyone of the combination.The process is repeated until the syndrome is matched. Table 3 illustrates the error location identification process. Table 2. Error location identification. H9 H10 H11 H12 XOR (H9, H10, H11, H12) S 0 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 The syndrome is matched with the XOR (H9, H10, H11, H12) combination according to Table 3, so error locations become [𝐷2, 𝑅𝐷3, 𝑅𝐷4, 𝑅𝐷5].The error occurred positions in R vector is [𝑅𝐷2, 𝑅𝐷3, 𝑅𝐷4, 𝑅𝐷5], which are equivalent to H vector positions as [H9, H10, H11, H12]. Finally, error correction operation is implemented by performing the complement of error corrected bits. The resultant error corrected outcome is obtained as follows 𝑂𝑢𝑡 = [0,0,1,0,1,0,1,1,1,0,1,1,1,0,0,1,1,0,0,1,1,1,1] 4. Results and discussions Xilinx ISE software was used to create all of the MBE – DCCdesigns. This software programmed gives two types of outputs: simulation and synthesis. The simulation results provide a thorough examination of the MBE – DCCarchitecture in terms of input and output byte level combinations. Decoding procedure approximated simply by applying numerous combinations of inputs and monitoring various outputs through simulated study of encoding correctness. The use of area in relation to the transistor count will be accomplished as a result of the synthesis findings. In addition, a time summary will be obtained with regard to various path delays, and a power summary will be prepared utilizing the static and dynamic power consumption. 114 VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications Figure 2. Simulation outcome of MBE-DCC. Figure 5 represents the simulation outcome of MBE-DCC. Here, data denotes the initial input (in), error_in is the manual error input, and enc_out denotes the encoded operand as a whole. The dec_out is the decoded output data that was error-free and is identical to the input data. Figure 3. Design summary. Figure 3 shows the design (area) summary of proposed method. Here, the proposed method utilizes the low area in terms of slice LUTs i.e., 55 out of available 17600. Figure 4. Time summary Figure 4 shows the time summary of proposed method. Here, the proposed method consumed total 0.321ns of time delay, which is entirely route delay. 115 Poongodi.S & Asoda Sunayana Rani Figure 5. Power summary. Figure 12 shows the power consumption report of propsoed MBE-DCC. Here, the proposed method consumed power as 1.065 watts. Table 4 compares the performance evaluation of various MBE-DCCapproches. Here, the propsoed MBE-DCCresulted in superior (reduced) performance in terms of LUTs, time-delay, and power consumption as compared to conventional approaches such as LBC [22], STBC [23], and Turbo [24]. Table 4. Performance evaluation. Metric LBC[22] STBC [23] Turbo[24] Proposed MBE-DCC LUTs 78 72 64 55 Time delay (ns) 3.28 2.284 1.453 0.321 Power consumption (w) 3.45 2.34 1.79 1.065 5. Conclusion The MBE-DCC for multiple bits error detection and correction is implemented in this work. The initial implementation of MBE-DCC encoding employs a generator matrix that has both identity bits and parity bits. Then, encoded data that has been corrupted by various noises and errors is transmitted into the space communication channel. Thus, using error location detection, syndrome detection, and error correction modules, the MBE-DCC decoding operation was carried out at the receiver side of space communications. The simulations showed that the proposed MBE-DCC performed better than traditional ECC techniques.This work can be extended with advanced multiple bit error detection and correction codes for real time applications. 116 VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications References [1] Somashekhar, Vikas Maheshwari, and R. P. Singh. "A Study of Fault Tolerance In High Speed VLSI Circuits." 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