Ece060214.qxd The Journal of Engineering Research Vol. 4, No.1 (2007) 69-74 1. Introduction Amplifiers for fiber-optic receivers require very high performance features in order to achieve the high gain, wideband, low noise characteristics required for optical communication systems. Some very elegant called "cur- rent-mode" optical transimpedance amplifiers (TIAs) using BiCMOS process have been reported (Halkias et al., 2000; Vansiri and Toumazou, 1995; Toumazou and Park, 1996). These TIAs are based on a common-base (CB) architecture, employing current shunt feedback. Two main advantages of the current-mode approach are the very wide bandwidth and the low-input resistance of the cir- cuit. This renders the amplifier bandwidth insensitive to the capacitance of the pin photodiode at the input. In pin photodiode receivers, the TIA has to achieve wide band _______________________________________ *Corresponding author’s e-mail: touatif@squ.edu.om width, low noise, high and accurate gain, and low power consumption. However, these requirements conflict with each other, requiring tradeoffs to be made to suit a partic- ular application. A current mode CB configuration has the potential to achieve simultaneously high bandwidth and high feedback resistors, potentially improving the ampli- fier gain and noise performance (Vansiri and Toumazou, 1995; Toumazou and Park, 1996; Ikeda et al. 2001). In this paper, new design approaches of BiCMOS-CB TIAs in a current-feedback configuration for high-speed optical communication applications are presented. The TIAs are design optimized for implementation with a standard, commercially available, 0.8-µm BiCMOS tech- nology. A detailed analysis on the effect of moving toward a more-FET based design is presented. The results are compared to recent similar designs. High-Performance BiCMOS Transimpedance Amplifiers for Fiber-Optic Receivers F. Touati*1 and M. Loulou2 *1 Department of Electrical and Computer Engineering, Sultan Qaboos University, P. O. Box 33, Al-Khoud 123, Muscat, Sultanate of Oman 2 Ecole Nationale d’Ingenieurs de Sfaz, Tunisie Received 14 February 2006; accepted 10 June 2006 Abstract: High gain, wide bandwidth, low noise, and low-power transimpedance amplifiers based on new BiCMOS com- mon-base topologies have been designed for fiber-optic receivers. In particular a design approach, hereafter called "A more- FET approach", added a new dimension to effectively optimize performance tradeoffs inherent in such circuits. Using con- ventional silicon 0.8 µm process parameters, simulated performance features of a total-FET transimpedance amplifier oper- ating at 7.2 GHz, which is close to the technology fT of 12 GHz, are presented. The results are superior to those of similar recent designs and comparable to IC designs using GaAs technology. A detailed analysis of the design architecture, includ- ing a discussion on the effects of moving toward more FET-based designs is presented. Keywords: Optical receiver, Transimpedance BiCMOS amplifier, 0.8µm silicon technology, Low power amplifier äɪeTransimpadenceBiCOMSá«Fƒ° dG ∑Ó°S’G ÈY ∫ÉÑ≤à°SG Iõ¡LC’ á«dÉY äÉØ°UGƒe äGP »JGƒàdG .±1ƒdƒd .Ω h2 áá°°UUÓÓÿÿGGGG äÉî° e º«ª°üJ ” :Transimpadence É«Lƒ∏æµJ ≈∏Y ~ªà©J I~j~LBiCOMS.áÑFƒ° dG ∑Ó°S’G ÈY ∫ÉÑ≤à°SG Iõ¡L’ ∂dPh ácΰûŸG I~YÉ≤dG hP »ª°ùJ »àdGh º«ª°üà∏d I~j~÷G á≤jô£dG âfÉch''''FET-approachre mo"A∂∏J ‘ á«©«Ñ£dG äGOÉ° àŸG ™e í‚CG áØ°üH πeÉ©àdG á«Ø«µd G~j~L G~©H âaÉ°VCG ~b ¿ƒµ«∏°ùdG É«Lƒ∏æµJ ΩG~îà°SÉHh .äɪŸGm0.8µ äɪe AGOCG ¢üFÉ°üÿ IÉcÉÙG èFÉàf ¢VôY ”total-FET OOôJ ≈∏Y π¨à°ûJ 7.2GHzøe áÑjôb »g »àdGh á∏ª©à°ùŸG É«Lƒ∏æµà∏d iƒ°ü≤dG ᪫≤dG.12GHzÉ«Lƒ∏æµJ Ω~îà°ùJ iôNCG ™e áHQÉ≤àeh É«Lƒ∏æµàdG ¢ùØæd áãj~M iôNG çÉëHG èFÉàf ¥ƒØJ É¡«∏Y π°üëàŸG èFÉàædG âfÉc GaAs ≈∏Y É«∏c ~ªà©j º«ª°üJ øe ÜGÎb’G ÒKÉJ á«Ø«c á°ûbÉæe ™e I~j~÷G äɪ«ª°üàdG ∂∏àd ™°Sƒe π«∏– ¢VôY ” áfG ɪc .ÌcG áØ∏µe øµdh ´ô°SG »g »àdGFET≈∏Y .äɪª∏d AGO’G ¢üFÉ°üN áá««MMÉÉààØØŸŸGG ääGGOOôôØØŸŸGG ºî° e ,»Fƒ°V ∫ÉÑ≤à°SG RÉ¡L :TransimpadenceBiCOMS ¿ƒµ«∏°ùdG É«Lƒ∏æµJ ,m0.8µ .áØ«©°V IQ~b ∂∏¡à°ùj ºî° e , 70 The Journal of Engineering Research Vol. 4, No.1 (2007) 69-74 2. Quantitative Description of Architecture The new CB topologies are shown in Figs. 1 and 2 (design 1 and 2), respectively. The basic architecture con- sists of a CB input stage Q1 followed by a common-source amplifier stage M2, and Q2 and Q3 are buffers. Another CB design reported in (Toumazou and Park, 1996) is also shown in Fig. 3 for comparison. What is special about the new designs compared to pre- vious CB schemes is that it is a total or quasi-FET based approach. That is, solely FETs are used to bias the ampli- fication stages (Q1 and M2). In the present designs (1 and 2), FET current mirrors are used to bias stages, where the initial current source of 5 mA must be very stable against external factors (temperature, biasing). Therefore, bandgap reference-based techniques must be used to implement that 5-mA current source. Also, the feedback resistor is connected from the output of Q2 via Rf to the input of M2 and not to the emitter of Q1 (ie. the amplifi- er input), as would be the conventional case. As a result, two straightforward advantages emerge: 1) the total power consumption is lower for the same gain and 2) these FETs should be sized in such a way to increase the gain while optimizing noise performance of the amplifier. This con- stitutes a new dimension added to optimize performance tradeoffs inherent in such designs while maintaining device processing yield high. The input transistor is a bipolar transistor. Therefore, the collector bias current required is less than the drain bias current required in a common-gate configuration for the same transconductance gm, hence leading to a lower- power consumption. Alternatively, for the same supply voltage the transconductance gm is higher in the bipolar transistor case and hence the noise contribution is lower. The amplifier stage is selected to be an FET (M2) because the input current noise is less than that of a bipolar transis- tor and because the optimum size can be selected. Going from design 3 via 2 to 1, the circuit becomes more and more FET-based. We will see what impact this would have on performance features. 3. DC Analysis The accurate prediction of the DC operating point of such circuits is of critical importance because the various stages are bias interdependent. Extensive DC analysis and optimization of the new CB design circuits was per- formed. The resistive shunt-feedback reduces the circuit sensitivity to external factors such as biasing, process tol- erances, and temperature. Also, the BJT at the input stage gives a higher transconductance for the same supply volt- age as explained above, resulting in two main advantages: 1) a higher transimpedance gain (hence low noise) and 2) a low input impedance (almost 1/gm1). The main objective to accommodate a low DC power consumption, a high transimpedance gain, low-noise, and to insure bias insen- sitivity within a relatively large range of supply voltages has been successively met. The positive and negative sup- ply voltages Vcc and Vee (in Figs. 1 and 2) can be varied within the range from +3.0 to 6.0 V and from -5.8 to -4.6 V, respectively, without degrading performance. The total DC power consumption (no load) for design 1, 2, and 3 is 56.6, 51.8, and 72.3 mW, respectively. This indicates that the new designs (1 and 2) are better optimized for low power consumption. Figure 1. BiCMOS CB TIA (design 1) Figure 2. BiCMOS CB TIA (design 2) Figure 3. BiCMOS common-base TIA (design 3) (Toumazou and Park, 1996) 71 The Journal of Engineering Research Vol. 4, No.1 (2007) 69-74 4. AC Analysis The common-base topology adopted makes the -3 dB bandwidth of the amplifier totally independent of the pho- todiode input capacitance, which determines only a non- dominant pole since the input resistance of M1 is small (Toumazou and Park, 1996). Figure 4 shows the small signal hybrid π model of the common-base transimpedance amplifier of Fig. 2 at high frequency. Here the base spreading resistances of bipolar junction transistors were neglected. The transfer function of this amplifier is governed by five major time constants: at the input (tin), associated with the Miller feedback resistance at the input of M2 (tRfMin), associated with the Miller feed- back resistance at the output of M2 (tRfMout), associated with the base-emitter capacitance of Q2 (tCbe2), and at the output (tout). Let us assume that tRfMin is the dominant time constant (which often has a much lower value) when compared to the other time constants. Therefore, the -3 dB bandwidth of the amplifier is approximately determined by the cut-off frequency as: (1) Therefore, by combining all the above equations Eq. (1) becomes: (2) The dominant pole of the amplifier, which determines the -3 dB bandwidth, depends mainly on the input capac- itance of M2 with Miller effect, the input capacitance of Q1, the drain capacitance of M4, and the feedback resistor Rf. Since M2 is a much smaller device, its net input capac- itance is small and hence Rf can be made larger for the same equivalent bandwidth, which would result in a lower overall noise. However, smaller device means higher resistance which would reduce the bandwidth. This would impose a careful sizing of M2 when dealing with the trade- off between low noise and wide bandwidth. On the other hand, M4 should be made narrow in order to reduce its noise contribution while preserving adequate bias collec- tor current for Q1. In Fig. 1, the size of M5, load of M2, can be selected to optimize Av2 for wide bandwidth. A critical aspect of the design phase was the optimiza- tion of the feedback resistor Rf as well as the size of the FET transistors in a tradeoff between gain, bandwidth, noise, and DC power consumption. It was shown (Abidi, 1988) that optimum noise per- formance may be obtained in transimpedance amplifiers employing submicron FET input stages by choosing the width of the input device such that its gate capacitance is one-fifth of the sum of the photodiode and stray capaci- tance. Based on this criterion, it was concluded that for design 1 (design 2), the optimum value of Rf = 2.3 kΩ (Rf = 2.1 kΩ) and W2 = 30 µm (W2 = 30 µm) for L = 0.8 ?m allow the desired transimpedance gain, minimum input noise current density, and low power consumption over the bandwidth of DC-7.2 GHz (4.4 GHz) to be achieved. This was obtained through successive cycles of DC and RF simulations. Simulated results of transimpedance gain of the new designs (1 and 2) are shown in Fig. 5. Also shown for comparison, the curve reported in (Toumazou and Park, 1996) (design 3). State-of-the-art 12 GHz fT silicon BiCMOS parts of a conventional 0.8-µm BiCMOS tech- nology were used. It can be seen that going toward a more FET-based configuration (ie. from design 3 via 2 to 1), the transimpedance gain as well as the -3 dB bandwidth improves. This trend is more prominent when one com- pares design 1 (thick solid line in Fig. 5) with design 3 (fine thin solid line in Fig. 5). This can be accounted for by the increasingly higher feedback resistor Rf = 1.4kΩ, 2.1kΩ, and 2.3kΩ which was achieved for design 3, 2, and 1, respectively. This would lead to a lower thermal noise contribution from the feedback resistor. This high transim- pedance gain is also due to using more and more active loads from design 3 to design 1 instead of resistive loads, since the closed-loop gain depends on Rf and the open- loop gain. fMinR dB3 t2 1 f π ≅− where: TCMinRfMinRt = with 2vA1 fR MinR + = . Av2 is the voltage gain of M2 and 2MinC2gsC4gdC1CTC +++= µ . The capacitance Cì 1 is the base-to-collector capacitance of Q1, Cgs2 and Cgd2 are the gate-to-source and gate-to- drain capacitances of M2, Cgd4 is the gate-to-drain capacitance of M4, and CMin2 is the Miller capacitance of the gate-to-drain capacitance Cgd2 of M2 at its input and given by ( ) 2gd2v2Min CA1C += . fT 2v dB3 RC2 )A1( f π + ≅− Figure 4. Small signal hybrid π model of the common-base amplifier of Fig. 2 72 The Journal of Engineering Research Vol. 4, No.1 (2007) 69-74 5. Noise Analysis The noise model, used to calculate the noise compo- nents, combines the conventional FET rms noise theory with the optical preamplifier (OEIC) noise theory (Minasian, 1987; Smith and Personick, 1980). The total input-referred equivalent noise current spectral density of designs 1 and 2 is approximately given by: (3) In Eq. (3), k is the Boltzmann constant, T is the absolute temperature, rbb1 is the base spreading resistance of Q1 (0.3 Ω), Cd is the capacitance of the pin photodiode (0.32 pF which is typical for a pin photodiode), rbe1 = kT/qIB1 with IB1 (27 uA) is the base current of Q1, Cbe1 (0.8 pF) is the base-emitter capacitance of Q1 and Cµ1 (defined above) = 0.2 pF, β1 (100) is the ac current gain of Q1, Ig2 is the gate leakage current of M2, Cgs2 = 1.0 pF, Cgd2 = Cgd4 = 0.3 pF, gm2 = 7.0 mS, gm4 = 15.0 mS, q is the elec- tron charge, Γ is the excess noise factor equal to 1.7 (Abidi, 1988) to account for the short-channel effects. The first three terms in Eq. (3) represent thermal noise contributions by Rf, RE1, and rbb1, respectively. The next two terms are base and collector shot noise current of Q1, the sixth term is noise contribution by gate leakage current of M2, which can be neglected (Halkias et al. 2000). The last two terms represent the channel thermal noises of M2 and M4, respectively. Figure 6 shows simulated results of the total rms input- referred noise current of the new designs, as calculated using Eq. (3) over a bandwidth of 10 GHz. Also shown for comparison, the results reported in (Toumazou and Park, 1996) (design 3). State-of-the-art 12 GHz fT silicon BiCMOS parts of a conventional 0.8 µm BiCMOS technology have been used. Two important features are clear. First, above around 5.0 GHz the new designs offer a lower total noise performance compared to that of (Toumazou and Park, 1996), whereas the opposite occurs otherwise. Second, Moving toward higher frequencies, the noise current becomes increasingly lower when we move toward a more FET-based design (solid line). This is important since the lower noise at higher frequencies offered by the total-FET based design will result in a lower BER at high data rates. Preliminary results showed that the addition of the inductor L = 2-15 nH (realizable monolithically as trans- mission lines) as shown in Fig. 1 results in a significant noise reduction. This can be explained by the reduction of noise contribution of M4 (last term in Eq. (3)) by adding the inductor. M4 noise spectral density with the inductor becomes: (4) From Eq. (4), with gm4 = 30 mS, and L = 15 nH, the inductor will reduce the noise spectral density of M4 by a factor of 1/3 at 1 GHz. Table 1 summarizes performance features of the new CB designs (1 and 2) and those of (Toumazou and Park, 1996). It is clear that the results obtained with the new CB designs are superior to those reported in (Toumazou and Park, 1996) and in (Park and Yoo, 2003). Also, these results are better than those reported in (Haralabidis et al., 2000) and fairly approach those obtained with GaAs MESFET and InP-HBT (Huber et al. 2000; Yoneyama et al. 2000; Minasian, 1987). Figure 5. Transimpedance gain versus frequency ( ) ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ +++ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ++++ + ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ++++ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ +++= 2 1bed 2 2 1E1 1be 1 1be4m 2 4gd12gs 2 2 f2m 2g 2 1bed 2 2 1E1 1be 1be 2 d 2 2 1E 1bb 1Ef eq )CC()f2( R 1kTr2rg )CCC()f2( R 1 g kT4 qI2CC)f2( R 1kTr2 r kT2 )C()f2( R 1 kTr4 R kT4 R kT4 )f(S π ββ π Γ π β π µ Figure 6. Total mean input-referred noise current versus frequency ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ++ + 2 1bed 2 2 1E1 1be 1 1be 2 4m 4m )CC()f2( R 1kTr2r )fL2g(1 g π ββπ 73 The Journal of Engineering Research Vol. 4, No.1 (2007) 69-74 Figure 7 shows the transient response of the previous CB TIA designs when driven by a 2.5 Gbps input current pulse train. It can be clearly seen that moving toward a more FET-based design, the output swing widens and the response becomes faster. Although the settling time in this case is bigger, still the response is faster and settles within the time frame of the driving pulses period. For the total-FET based design (thick solid line), the response clearly reaches 200 mV output swing for a 100 µA input current. According to that, one can expect a sufficiently open eye diagram at 2.5 Gbps for NRZ synchronous links. Noise simulations of the new designs have also been conducted using 0.6 µm BiCMOS process parameters. Results showed even lower total rms noise current; more than 1 dB lower in the frequency range above 4.0 GHz. This may indicate the validity of the new design approach for shorter channels also. Further investigations are in order in this regard. 6. Conclusions High-performance BiCMOS common-base transim- pedance amplifiers for fiber-optic receivers have been improved. In particular, a more FET-based approach was found effective in potentially optimizing performance fea- tures. Simulated results showed improved transimpedance gain, noise characteristics, bandwidth, and power con- sumption when compared to recent similar designs. A transimpedance gain as high as 65.2 dB over a bandwidth of 7.2 GHz, which is close to the technology fT of 12 GHz, was achieved. The 3.5 GHz and 7.0 GHz total equivalent input-referred noise current have been minimized to achieve 17.7 and 28.7 pA/Hz0.5, respectively. Also the total power consumption of the circuit was optimized to 56.6 mW. These performance features are fairly compara- ble to those reported using GaAs MESFET. While optimizing the design for gain, noise and power, little attention has been given to dynamic range and out- put swing. However, now that the new approach is demonstrated, much study is aimed at optimizing other performance features. Acknowledgments The author wish to thank Sultan Qaboos University (SQU) for providing the facilities and resources. Also, the authors wish to thank the Tunisian Ministry of Scientific Research Technology and Development of competencies for its support and grant in the frame of the program of cooperation with the Tunisian researchers abroad. References Abidi, A., 1988, "On the Choice of Optimum FET Size in Wide-band Transimpedance Amplifiers," J. of Lightwave Technology, Vol. 6(1), pp. 64-66. Halkias, G., Haralabidis, N., Kyriakis-Bitzaros, E. D. and Katsafouros, S., 2000, "1.7 GHz Bipolar Optoelectronic Receiver using Conventional 0.8?m BiCMOS Process," IEEE Int. Symp. on Circuits & Systems, pp. V417-V420. Haralabidis, N., Katsafouros, S. and Halkias, G., 2000, "A 1 GHz CMOS Transimpedance Amplifier for Chip- to-chip Optical Interconnects," IEEE Int. Symp. On Circuits & Systems, pp. V421-V424. Huber, D., Bauknecht, R., Bergamaschi, C., Bitter, M., Huber, A., Morf, T., Neiger, A., Rohner, M., Schnyder, I., Schwarz, V. and Jackel, H., 2000, "InP- InGaAs Single HBT Technology for Photoreceiver OEIC's at 40 Gb/s and beyond," J. of Lightwave Technology, Vol. 18, pp. 992-999. Ikeda, H., Ohshima, T., Tsunotani, M., Ichioka, T. and Kimura, T., 2001, "An Auto-gain Control Transimpedance Amplifier with low Noise and wide input Dynamic Range 10-Gb/s Optical Communication Systems," IEEE J. of Solid-State Circuits, Vol. 36(9), pp. 1303-1308. Minasian, R., 1987, "Optimum Design of a 4Gbit/s GaAs MESFET Optical Preamplifier," J. of Lightwave Technology, Vol. LT-5(3), pp. 373-379. Park, S. and Yoo, H., 2003, "2.5 Gbit/s CMOS transim- pedance amplifier for optical communication applica- tions," Electronics Letters, Vol. 39(2), pp. 211-212. Gai n (dB) BW (GHz) Noise (pA/Hz0.5) @ 3.5 7 GHz Total Power (mW) New Design 1 65.2 7.2 17.7 28.7 56.6 New Design 2 62.1 4.4 18.3 29.4 51.8 Design 3 [3] 59.8 4.2 15.2 35.5 72.3 Table 1. BiCMOS CB TIA design parameters Figure 7. Transient response of the CB BiCMOS TIAs at 2.5 Gbps for a 100µA pulse input current signal 74 The Journal of Engineering Research Vol. 4, No.1 (2007) 69-74 Smith, R. and Personick, S., 1980, "Receiver Design for Optical Fiber Communication Systems", Chapter 4. Publisher: Springer-Verlag. Toumazou, C. and Park, S., 1996, "Wideband Low Noise CMOS Transimpedance Amplifier for Gigahertz Operation," Electronics Letters, Vol. 32(13), pp. 1194-1996. Vansiri, T. and Toumazou, C., 1995, "Integrated High Frequency Low-noise Curret-mode Optical Transimpedance Preamplifiers: Theory and Practice," IEEE J. of Solid-State Circuits, Vol. 30(6), pp. 677- 685. Yoneyama, M., Miyamoto, Y., Otsuji, T., Toba, H., Yamane, Y., Ishibashi, T. and Miyazawa, H., 2000, "Fully Electrical 40Gb/s TDM System Prototype Based InP HEMT Digital IC Technologies," J. of Lightwave Technology, Vol. 18, pp. 34-43.